公开(公告)号：US20130062758A1

公开(公告)日：2013-03-14

申请号：US13422424

申请日：2012-03-16

Applicant: Takashi IMOTO ,  Yoriyasu Ando ,  Akira Tanimoto ,  Masaji Iwamoto ,  Yasuo Takemoto ,  Hideo Taguchi ,  Naoto Takebe ,  Koichi Miyashita ,  Jun Tanaka ,  Katsuhiro Ishida ,  Shogo Watanabe ,  Yuichi Sano

Inventor： Takashi IMOTO ,  Yoriyasu Ando ,  Akira Tanimoto ,  Masaji Iwamoto ,  Yasuo Takemoto ,  Hideo Taguchi ,  Naoto Takebe ,  Koichi Miyashita ,  Jun Tanaka ,  Katsuhiro Ishida ,  Shogo Watanabe ,  Yuichi Sano

IPC: H01L25/07 ,  H01L23/48

CPC classification number: H01L23/3135 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a semiconductor device has a substrate, a first semiconductor chip, an electrode, a first and second connection member, and a first and second sealing member. The electrode is disposed on the first semiconductor chip and contains Al. The first connection member electrically connects the electrode and the substrate and contains Au or Cu. The first sealing member seals the first semiconductor chip and the first connection member. One or more second semiconductor chips are stacked on the first sealing member. The second sealing member seals the first connection member, the one or more second semiconductor chips, and the one or more second connection members. A ratio of a total weight W1 of Cl ions and Br ions in the first sealing member to a weight W0 of resins of the substrate and the first sealing member is 7.5 ppm or lower.

Abstract translation: 在一个实施例中，半导体器件具有衬底，第一半导体芯片，电极，第一和第二连接构件以及第一和第二密封构件。 电极设置在第一半导体芯片上并且包含Al。 第一连接构件电连接电极和衬底并且包含Au或Cu。 第一密封构件密封第一半导体芯片和第一连接构件。 一个或多个第二半导体芯片堆叠在第一密封构件上。 第二密封构件密封第一连接构件，一个或多个第二半导体芯片和一个或多个第二连接构件。 第一密封部件中的Cl离子和Br离子的总重量W1与基板和第一密封部件的树脂的重量W0的比例为7.5ppm以下。

公开(公告)号：US20120153471A1

公开(公告)日：2012-06-21

申请号：US13235408

申请日：2011-09-18

Applicant: Takeshi WATANABE ,  Yuji Karakane ,  Takashi Imoto

Inventor： Takeshi WATANABE ,  Yuji Karakane ,  Takashi Imoto

IPC: H01L23/485

CPC classification number: H01L23/3128 ,  H01L21/566 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device according to the present embodiment includes a substrate including wirings. At least one first semiconductor chip is mounted on a first surface of the substrate and is electrically connected to any of the wirings. A first metal ball is provided on the first surface of the substrate and is electrically connected to the first semiconductor chip through any of the wirings. A first resin seals the wirings, the first semiconductor chip, and the first metal ball on the first surface of the substrate. A top of the first metal ball protrudes from a surface of the first resin and is exposed.

Abstract translation: 根据本实施例的半导体器件包括包括布线的衬底。 至少一个第一半导体芯片安装在基板的第一表面上并且电连接到任何布线。 第一金属球设置在基板的第一表面上，并且通过任何布线与第一半导体芯片电连接。 第一树脂在衬底的第一表面上密封布线，第一半导体芯片和第一金属球。 第一金属球的顶部从第一树脂的表面突出并暴露。

公开(公告)号：US20110309502A1

公开(公告)日：2011-12-22

申请号：US13052368

申请日：2011-03-21

Applicant: Yuichi SANO ,  Takashi Imoto ,  Naoto Takebe ,  Katsuhiro Ishida ,  Tomomi Honda ,  Yasushi Kumagai

Inventor： Yuichi SANO ,  Takashi Imoto ,  Naoto Takebe ,  Katsuhiro Ishida ,  Tomomi Honda ,  Yasushi Kumagai

IPC: H01L23/49 ,  H01L21/60 ,  H01L21/44

CPC classification number: H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48476 ,  H01L2224/4848 ,  H01L2224/48599 ,  H01L2224/48992 ,  H01L2224/48997 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49429 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  Y10T29/41 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.

Abstract translation: 根据一个实施例，半导体器件包括第一半导体元件，第一电极，球形部分，第二电极和线。 第一电极电连接到第一半导体元件。 球部设置在第一电极上。 导线连接球部和第二电极。 在与第二电极相反的一侧的线的端部处的折回部分的厚度小于导线的直径。

公开(公告)号：US20080012892A1

公开(公告)日：2008-01-17

申请号：US11773957

申请日：2007-07-05

Applicant: Takashi Imoto

Inventor： Takashi Imoto

IPC: B41J29/393 ,  G08B21/00

CPC classification number: G06K15/00 ,  G06K15/002

Abstract: When the condition information of a printing apparatus contains a plurality of error/warning information, the printing apparatus determines the priority orders of the error/warning information and whether the plurality of error/warning information are to be notified, based on the print setting information of input print data. Based on the determination result, the printing apparatus generates status information which contains the plurality of error/warning information, their priority order and notification necessary/unnecessary information representing whether the plurality of error/warning information are to be notified. The printing apparatus displays display information corresponding to the error/warning information on the display unit, based on the plurality of error/warning information, their priority orders and the notification necessary/unnecessary information in the generated status information.

Abstract translation: 当打印装置的条件信息包含多个错误/警告信息时，打印装置基于打印设置信息确定错误/警告信息的优先顺序以及是否要通知多个错误/警告信息 的输入打印数据。 基于该确定结果，打印装置生成包含多个错误/警告信息，其优先级顺序和表示是否要通知多个错误/警告信息的必要/不必要的信息的状态信息。 打印装置基于生成的状态信息中的多个错误/警告信息，其优先级顺序和通知必要/不必要的信息，在显示单元上显示与错误/警告信息相对应的显示信息。

公开(公告)号：US20060055061A1

公开(公告)日：2006-03-16

申请号：US11216144

申请日：2005-09-01

Applicant: Ryuji Hosokawa ,  Takashi Imoto

Inventor： Ryuji Hosokawa ,  Takashi Imoto

IPC: H01L23/48

CPC classification number: H01L24/06 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4824 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate having first and second surfaces, the substrate having an opening; a first adhesive layer provided on the first surface; a second adhesive layer provided under the second surface; a third adhesive layer provided around the opening; a semiconductor chip arranging a plurality of chip bonding pads in a central portion of the semiconductor chip and adhered on the third adhesive layer; substrate bonding pads adhered under the second adhesive layer; bonding wires connecting the chip bonding pads to the substrate bonding pads; and an encapsulating resin provided around the semiconductor chip.

Abstract translation: 半导体器件包括具有第一和第二表面的衬底，衬底具有开口; 设置在第一表面上的第一粘合剂层; 设置在所述第二表面下方的第二粘合剂层; 围绕所述开口设置的第三粘合剂层; 半导体芯片，其在所述半导体芯片的中心部分布置多个芯片焊盘并粘附在所述第三粘合剂层上; 衬底粘合垫粘附在第二粘合剂层下面; 将芯片接合焊盘连接到衬底接合焊盘的接合线; 以及设置在半导体芯片周围的封装树脂。

公开(公告)号：US20050254084A1

公开(公告)日：2005-11-17

申请号：US10522625

申请日：2003-08-25

Applicant: Takashi Imoto

Inventor： Takashi Imoto

IPC: G06F3/12 ,  G06F9/46 ,  G06K1/00 ,  G06F15/00

CPC classification number: G06F3/1207 ,  G06F3/1218 ,  G06F3/1229 ,  G06F3/1259 ,  G06F3/1285

Abstract: As an example of an embodiment, there is disclosed a notifying method of notifying the user of information regarding an apparatus in an information processing apparatus which can simultaneously provide an environment, as a user session, which can activate a user's desired program to each of a plurality of users. This method has: an obtaining step of obtaining the information regarding the apparatus; a specifying step of specifying the user session which uses a display unit of the information processing apparatus; and an activating step of activating a display program for displaying the information obtained in the obtaining step by the user session specified in the specifying step.

Abstract translation: 作为实施例的示例，公开了一种通知用户有关信息处理设备中的装置的信息的通知方法，其可以同时提供作为用户会话的环境，其可以激活用户期望的节目 多个用户。 该方法具有获取与该装置有关的信息的获取步骤; 指定使用信息处理装置的显示单元的用户会话的指定步骤; 以及激活步骤，用于激活显示程序，用于显示在指定步骤中指定的用户会话在获取步骤中获得的信息。

公开(公告)号：US20050063651A1

公开(公告)日：2005-03-24

申请号：US10898337

申请日：2004-07-26

Applicant: Hiroshi Hamasaki ,  Hideto Furuyama ,  Hideo Numata ,  Takashi Imoto

Inventor： Hiroshi Hamasaki ,  Hideto Furuyama ,  Hideo Numata ,  Takashi Imoto

IPC: G02B6/42 ,  H01L31/0232 ,  H01L33/08 ,  H01L33/56 ,  H01L33/62 ,  H01L29/10

CPC classification number: G02B6/4249 ,  G02B6/423

Abstract: An optical semiconductor module comprises an optical transmission channel including a waveguide transmitting a light beam, a holding member whose holding member holds the channel with the end of the channel being exposed from the surface, electric wiring formed on the surface, an optical semiconductor element, mounted above the surface, including an active area to emit or receive a light beam and an electrode pad electrically connected to the electric wiring, the active area optically coupled to the waveguide at the end of the channel, and an electrical insulation film between the optical semiconductor element and the holding member, including openings each corresponding to an electrical connection between the electrode pad and the electric wiring, and an optically coupling portion between the active area and the waveguide, the electrical insulation film being in contact with a portion of the end of the channel.

Abstract translation: 光学半导体模块包括：光传输通道，其包括透射光束的波导;保持部件，其保持部件保持沟道的端部从表面露出，形成在表面上的电布线，光学半导体元件， 安装在所述表面上方，包括发射或接收光束的有源区域和电连接到所述电线路的电极焊盘，所述有源区域在所述通道的端部处光耦合到所述波导，以及在所述光学器件之间的电绝缘膜 半导体元件和保持构件，包括各自对应于电极焊盘和电布线之间的电连接的开口以及有源区域和波导之间的光学耦合部分，电绝缘膜与端部的一部分接触 的频道。

公开(公告)号：US06617678B2

公开(公告)日：2003-09-09

申请号：US10145722

申请日：2002-05-16

Applicant: Takashi Yamazaki ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Katsuhiko Oyama ,  Takashi Imoto ,  Mikio Matsui

Inventor： Takashi Yamazaki ,  Mitsuyoshi Endo ,  Chiaki Takubo ,  Katsuhiko Oyama ,  Takashi Imoto ,  Mikio Matsui

IPC: H01L2302

CPC classification number: H01L25/0657 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.

公开(公告)号：US20120257242A1

公开(公告)日：2012-10-11

申请号：US13437388

申请日：2012-04-02

Applicant: Takashi Imoto

Inventor： Takashi Imoto

IPC: G06K15/02

CPC classification number: G06F3/1222 ,  G06F3/1238 ,  G06F3/1239 ,  G06F3/1267 ,  G06F21/10 ,  G06F21/608

Abstract: An information processing apparatus and method includes determining whether print data is limited in a number of times of printing, determining whether a setting of storing the print data in the information processing apparatus is valid, and stopping transmission of the print data in a case where it is determined that the print data is limited in the number of times of printing and it is determined that the setting is valid.

Abstract translation: 一种信息处理装置和方法，包括：确定打印数据是否在多次打印中被限制，确定在信息处理装置中存储打印数据的设置是否有效，以及在其中的情况下停止打印数据的传送 确定打印数据被限制在打印次数中，并且确定该设置有效。

公开(公告)号：US07932605B2

公开(公告)日：2011-04-26

申请号：US11889071

申请日：2007-08-08

Applicant: Takashi Imoto ,  Chiaki Takubo

Inventor： Takashi Imoto ,  Chiaki Takubo

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L24/34 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/37 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/82 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/86 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: There is disclosed a semiconductor device comprising at least one semiconductor element, one chip mounting base being provided at least one first interconnection on one major surface thereof and at least one second interconnection on the other major surface thereof, and the semiconductor element being electrically connected to at least the one first interconnection and mounted on the one major surface, a sealing member being provided on the one major surface of the chip mounting base and covering the semiconductor element and the first interconnection, at least one third interconnection being provided on a surface of the sealing member, and at least one fourth interconnection being provided in the sealing member and the chip mounting base, and electrically connected to the first interconnection, the second interconnection, and the third interconnection.

Abstract translation: 公开了一种包括至少一个半导体元件的半导体器件，一个芯片安装基座在其一个主表面上设置有至少一个第一互连件和在其另一个主表面上的至少一个第二互连件，并且该半导体元件电连接到 至少一个第一互连并且安装在所述一个主表面上，密封构件设置在所述芯片安装基座的所述一个主表面上并且覆盖所述半导体元件和所述第一互连，至少一个第三互连设置在 所述密封构件和至少一个第四互连件设置在所述密封构件和所述芯片安装基座中，并且电连接到所述第一互连，所述第二互连和所述第三互连。