公开(公告)号：US20090184407A1

公开(公告)日：2009-07-23

申请号：US12015754

申请日：2008-01-17

Applicant: Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

Inventor： Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

IPC: H01L21/70 ,  H01L23/02

CPC classification number: H05K3/3436 ,  H01L21/56 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H05K3/225 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract translation: 由此制造的方法和返工的中间和合成的电子模块，由此将需要返工的部件放置并从模块移除，以露出位于底部填充基质内的封装的焊料连接。 焊接连接和底部填充基体的高度减小，随后将焊料从焊料连接处蚀刻出来，以在底部填充基体内形成开口。 然后除去底部填充材料以暴露基底的冶金。 具有具有焊接连接阵列的释放层的坯料与暴露的冶金学对准，并且该焊料阵列从坯料转移到冶金上。 然后，使用热和压力将转移的焊接连接件平坦化，然后将新部件的焊接连接件连接到扁平焊接连接，并对位于新芯片和基板之间的这些返工焊接点进行底部填充。

公开(公告)号：US07781232B2

公开(公告)日：2010-08-24

申请号：US12015754

申请日：2008-01-17

Applicant: Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

Inventor： Charles L. Arvin ,  Benjamin V. Fasano ,  Mario J. Interrante ,  Glenn A. Pomerantz

IPC: H01L21/48 ,  H01L21/00

CPC classification number: H05K3/3436 ,  H01L21/56 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/09701 ,  H05K3/225 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/176 ,  Y02P70/613 ,  H01L2924/00

Abstract: Methods and reworked intermediate and resultant electronic modules made thereby, whereby a component in need of rework is located and removed from the module to reveal encapsulated solder connections residing within an underfill matrix. Heights of both the solder connections and underfill matrix are reduced, followed by etching the solder out of the solder connections to form openings within the underfill matrix. The underfill material is then removed to expose metallurgy of the substrate. A blank having a release layer with an array of solder connections is aligned with the exposed metallurgy, and this solder array is transferred from the blank onto the metallurgy. The transferred solder connections are then flattened using heat and pressure, followed by attaching solder connections of a new component to the flattened solder connections and underfilling these reworked solder connections residing between the new chip and substrate.

Abstract translation: 由此制造的方法和返工的中间和合成的电子模块，由此将需要返工的部件放置并从模块移除，以露出位于底部填充基质内的封装的焊料连接。 焊接连接和底部填充基体的高度减小，随后将焊料从焊料连接处蚀刻出来，以在底部填充基体内形成开口。 然后除去底部填充材料以暴露基底的冶金。 具有具有焊接连接阵列的释放层的坯料与暴露的冶金学对准，并且该焊料阵列从坯料转移到冶金上。 然后，使用热和压力将转移的焊接连接件平坦化，然后将新部件的焊接连接件连接到扁平焊接连接，并对位于新芯片和基板之间的这些返工焊接点进行底部填充。

公开(公告)号：US20070158395A1

公开(公告)日：2007-07-12

申请号：US11306779

申请日：2006-01-11

Applicant: Benjamin V. Fasano ,  Mario J. Interrante

Inventor： Benjamin V. Fasano ,  Mario J. Interrante

IPC: B23K31/02

CPC classification number: B23K1/0008 ,  B23K2101/42

Abstract: A method to form solder microsockets on a first substrate (for example a chip carrier) so that when the first substrate is aligned with a second substrate having shaped solder elements (for example a semiconductor device), the shaped solder elements fit into the solder microsockets. At least one of the aligned solder elements and solder microsockets may be reflowed to effect joining of the first and second substrates.

Abstract translation: 一种在第一衬底（例如芯片载体）上形成焊料微插座的方法，使得当第一衬底与具有成形焊料元件（例如半导体器件）的第二衬底对准时，成形焊料元件装配到焊料微插槽中 。 对准的焊料元件和焊料微插座中的至少一个可以回流以实现第一和第二衬底的接合。

公开(公告)号：US20110044369A1

公开(公告)日：2011-02-24

申请号：US12544696

申请日：2009-08-20

Applicant: Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

Inventor： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC: H01S5/18 ,  H01L31/0232 ,  H01L23/34 ,  H01L21/50

CPC classification number: H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract translation: 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US07250576B2

公开(公告)日：2007-07-31

申请号：US10908615

申请日：2005-05-19

Applicant: Evan G. Colgan ,  David L. Edwards ,  Benjamin V. Fasano ,  Kamal K. Sikka ,  Jeffrey A. Zitz ,  Wei Zou

Inventor： Evan G. Colgan ,  David L. Edwards ,  Benjamin V. Fasano ,  Kamal K. Sikka ,  Jeffrey A. Zitz ,  Wei Zou

IPC: H05K1/16

CPC classification number: H01L23/04 ,  H01L23/3675 ,  H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83051 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: A chip package including a chip extension for containing thermal interface material (TIM) and improves chip cooling, and a related method, are disclosed. In particular, the chip package includes a chip, a cooling structure coupled to the chip via a TIM, and a chip extension may be thermally coupled to an outer edge of the chip. A TIM placed between the chip and the cooling structure is contained during thermal cycling by the chip extension such that void formation at the edge of the chip, which can move between the chip and cooling structure, is suppressed. The chip extension also improves lateral heat dissipation by providing a greater thermal contact area between the cooling structure and the chip and, if needed, the substrate at a much lower cost than using larger die with lower production unit output from a wafer.

Abstract translation: 公开了一种包括用于包含热界面材料（TIM）并提高芯片冷却的芯片延伸的芯片封装以及相关方法。 特别地，芯片封装包括芯片，经由TIM耦合到芯片的冷却结构，并且芯片延伸部可热耦合到芯片的外边缘。 放置在芯片和冷却结构之间的TIM被芯片延伸部的热循环期间包含，从而可以抑制可在芯片和冷却结构之间移动的芯片边缘处的空隙形成。 芯片延伸还通过在冷却结构和芯片之间提供更大的热接触面积，并且如果需要，以比使用具有较低的晶片生产单位输出的较大模具的成本低得多的成本来改善侧向散热。

公开(公告)号：US06436332B1

公开(公告)日：2002-08-20

申请号：US09705139

申请日：2000-11-02

Applicant: Benjamin V. Fasano ,  Robert A. Rita

Inventor： Benjamin V. Fasano ,  Robert A. Rita

IPC: C04B35195

CPC classification number: C03C14/004 ,  C03C2214/08 ,  C03C2214/20 ,  H05K1/0306 ,  Y10T428/24926

Abstract: The dielectric constant of low loss tangent glass-ceramic compositions, such as cordierite-based glass ceramics, is modified over a range by selective addition of high dielectric constant ceramics, such as titanates, tantalates and carbides and metals, such as copper. The low loss tangent is retained or improved over a range of frequencies, and the low CTE of the glass-ceramic is maintained. BaTiO3, SrTiO3 and Ta2O5 produce the most effective results.

Abstract translation: 通过选择性地添加高介电常数陶瓷，例如钛酸盐，钽酸盐，碳化物和金属如铜，可以在一定范围内改变低损耗相切玻璃 - 陶瓷组合物的介电常数，例如堇青石系玻璃陶瓷。 在一定范围的频率范围内保持或改善低损耗角正切，保持玻璃陶瓷的低CTE。 BaTiO3，SrTiO3和Ta2O5产生最有效的结果。

公开(公告)号：US06354844B1

公开(公告)日：2002-03-12

申请号：US09459552

申请日：1999-12-13

Applicant: Patrick A. Coico ,  Benjamin V. Fasano

Inventor： Patrick A. Coico ,  Benjamin V. Fasano

IPC: H01R1200

CPC classification number: H05K3/325 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01R12/52 ,  H05K3/303 ,  H01L2224/0401

Abstract: A Land Grid Array electronic package having an array of contact pads is connected to a corresponding array of contact pads on a circuit board through a matching array of conductive pins of a flexible interposer. Alignment of the electronic package to the flexible interposer and flexible interposer to the circuit board is obtained by registration of alignment components to the contact pads and conductive pins. A pair of alignment components, such as pin-like alignment structures, on selected pads of both the electronic package and circuit board mate within alignment holes at the sites of corresponding pin locations in said flexible interposer. Alternatively, the pin-like alignment structures on the electronic package can be extended to pass through the said alignment holes of said flexible interposer into alignment holes which replace the pin-like alignment structure on said circuit board.

Abstract translation: 具有接触焊盘阵列的焊盘阵列电子封装通过柔性插入器的导电引脚的匹配阵列连接到电路板上的相应的接触焊盘阵列。 通过将对准部件配准到接触焊盘和导电销来获得电子封装与柔性插入件和柔性插入件到电路板的对准。 在电子封装和电路板的选定焊盘上的一对对准部件，例如针状对准结构，在所述柔性插入器中的相应引脚位置的位置处的对准孔内匹配。 或者，可以将电子封装上的针状对准结构延伸穿过所述柔性插入件的所述对准孔，以对准替代所述电路板上的针状对准结构的对准孔。

公开(公告)号：US06187418B1

公开(公告)日：2001-02-13

申请号：US09356944

申请日：1999-07-19

Applicant: Benjamin V. Fasano ,  David H. Gabriels ,  Richard F. Indyk ,  Sundar M. Kamath ,  Scott I. Langenthal ,  Srinivasa S. N. Reddy ,  Rao V. Vallabhaneni

Inventor： Benjamin V. Fasano ,  David H. Gabriels ,  Richard F. Indyk ,  Sundar M. Kamath ,  Scott I. Langenthal ,  Srinivasa S. N. Reddy ,  Rao V. Vallabhaneni

IPC: B32B300

CPC classification number: H05K3/4092 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/4053 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09781 ,  H05K2201/0979 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: Disclosed is a multilayer ceramic substrate having an outer pad, for example an I/O pad, which is anchored to an inner pad of the multilayer ceramic substrate by either a plurality of vias or one large via. The outer pad and vias are made of high metal material, preferably 100% metal, so they won't adhere very well to the ceramic substrate. The inner pad is a composite metal/ceramic material which will bond very well to the ceramic substrate.

Abstract translation: 公开了一种多层陶瓷基板，其具有外焊盘，例如I / O焊盘，其通过多个通孔或一个大通孔锚定到多层陶瓷基板的内焊盘。 外垫和通孔由高金属材料制成，优选为100％金属，因此它们将不能很好地粘附到陶瓷基片上。 内垫是复合金属/陶瓷材料，其将很好地结合到陶瓷基底上。

公开(公告)号：US5552232A

公开(公告)日：1996-09-03

申请号：US361351

申请日：1994-12-21

Applicant: Jon A. Casey ,  Carla N. Cordero ,  Benjamin V. Fasano ,  David B. Goland ,  Robert Hannon ,  Jonathan H. Harris ,  Lester W. Herron ,  Gregory M. Johnson ,  Niranjan M. Patel ,  Andrew M. Reitter ,  Subhash L. Shinde ,  Rao V. Vallabhaneni ,  Robert A. Youngman

Inventor： Jon A. Casey ,  Carla N. Cordero ,  Benjamin V. Fasano ,  David B. Goland ,  Robert Hannon ,  Jonathan H. Harris ,  Lester W. Herron ,  Gregory M. Johnson ,  Niranjan M. Patel ,  Andrew M. Reitter ,  Subhash L. Shinde ,  Rao V. Vallabhaneni ,  Robert A. Youngman

IPC: B32B18/00 ,  B22F7/02 ,  C04B35/581 ,  C04B37/02 ,  C04B41/51 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C29/16 ,  H01L21/48 ,  H01L23/373 ,  H05K1/03 ,  H05K3/24 ,  H05K3/40 ,  H05K3/46 ,  B22F3/00

CPC classification number: C04B41/009 ,  B22F7/02 ,  C04B41/5133 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C22C29/16 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3731 ,  H05K3/4061 ,  B22F2998/00 ,  C04B2111/00405 ,  C04B2111/00844 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/035 ,  H05K2201/09981 ,  H05K3/248 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T428/12021 ,  Y10T428/12028 ,  Y10T428/12056 ,  Y10T428/31678

Abstract: Disclosed is an aluminum nitride body having graded metallurgy and a method for making such a body. The aluminum nitride body has at least one via and includes a first layer in direct contact with the aluminum nitride body and a second layer in direct contact with, and that completely encapsulates, the first layer. The first layer includes 30 to 60 volume percent aluminum nitride and 40 to 70 volume percent tungsten and/or molybdenum while the second layer includes 90 to 100 volume percent of tungsten and/or molybdenum and 0 to 10 volume percent of aluminum nitride.

公开(公告)号：US08559474B2

公开(公告)日：2013-10-15

申请号：US13604341

申请日：2012-09-05

Applicant: Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

Inventor： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC: H01S5/024 ,  H01S5/18 ,  H01L23/28 ,  H01L23/18

CPC classification number: H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

Abstract: An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Abstract translation: 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。