公开(公告)号：US08904632B2

公开(公告)日：2014-12-09

申请号：US13242155

申请日：2011-09-23

申请人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Casey P. Rodriguez

发明人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Casey P. Rodriguez

IPC分类号： H01K3/10 ,  H05K3/46 ,  H05K3/42

CPC分类号： H05K1/0298 ,  H05K1/09 ,  H05K1/116 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/0141 ,  H05K2201/09545 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method is for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions together.

摘要翻译： 一种用于从电路板层制造多层电路板的方法，每个电路板包括介电层和其上包括第一金属的导电迹线。 该方法包括在第一电路板层中形成通孔，将通孔与第一金属电镀，并将第二金属涂覆在第一电路板层的第一金属上，镀通孔和第一金属 金属。 该方法还包括将第一和第二电路板层对准在一起，使得第一电路板层的电镀通孔与第二电路板层上的特征相邻，并且加热并压紧对准的第一和第二电路板层 以将电介质层层叠在一起，并将相邻的金属部分结合在一起的第一和第二金属的金属间化合物。

公开(公告)号：US09142497B2

公开(公告)日：2015-09-22

申请号：US13253388

申请日：2011-10-05

申请人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Robert Patrick Maloney ,  David M. Smith

发明人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Robert Patrick Maloney ,  David M. Smith

IPC分类号： H05K3/36 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H01L23/66

CPC分类号： H01P3/121 ,  H01L21/4846 ,  H01L23/498 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H05K3/4614 ,  H05K3/4697 ,  H05K2201/0141 ,  H05K2203/016 ,  H05K2203/308 ,  H01L2924/00

摘要： A method has been described for making an electrical structure having an air dielectric and includes forming a first subunit including a sacrificial substrate, an electrically conductive layer including a first metal on the sacrificial substrate, and a sacrificial dielectric layer on the sacrificial substrate and the electrically conductive layer. The method further includes forming a second subunit including a dielectric layer and an electrically conductive layer thereon including the first metal, and coating a second metal onto the first metal of one or more of the first and second subunits. The method also includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate and sacrificial dielectric layer to thereby form the electrical structure having the air dielectric.

摘要翻译： 已经描述了一种用于制造具有空气电介质的电结构的方法，并且包括形成包括牺牲衬底的第一子单元，在牺牲衬底上包括第一金属的导电层和牺牲衬底上的牺牲电介质层， 导电层。 该方法还包括在其上形成包括电介质层和其上的导电层的第二子单元，其上包括第一金属，并且将第二金属涂覆到第一和第二子单元中的一个或多个的第一金属上。 该方法还包括将第一和第二子单元对齐在一起，加热和压制对准的第一和第二子单元以形成将相邻金属部分粘合在一起的第一和第二金属的金属间化合物，以及去除牺牲基底和牺牲介电层从而形成 电气结构具有空气电介质。

公开(公告)号：US08539666B2

公开(公告)日：2013-09-24

申请号：US13293671

申请日：2011-11-10

申请人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Robert Patrick Maloney ,  David M. Smith

发明人： Michael Raymond Weatherspoon ,  Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Robert Patrick Maloney ,  David M. Smith

IPC分类号： H01F7/06

CPC分类号： H01F27/2804 ,  H01F5/00 ,  H01F17/0006 ,  H01F41/041 ,  H01F2017/0046 ,  H01F2017/0073 ,  H05K1/165 ,  H05K3/146 ,  H05K3/16 ,  H05K3/20 ,  H05K2201/0141 ,  H05K2201/0305 ,  H05K2201/1003 ,  H05K2203/016 ,  Y10T29/4902 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075

摘要： A method is for making an electrical inductor. The method includes forming a first subunit having a sacrificial substrate, and an electrically conductive layer defining the electrical inductor and including a first metal on the sacrificial substrate. The method includes forming a second subunit having a dielectric layer and an electrically conductive layer thereon defining electrical inductor terminals and having the first metal, and coating a second metal onto the first metal of one of the first and second subunits. The method includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate.

公开(公告)号：US08778124B2

公开(公告)日：2014-07-15

申请号：US12016060

申请日：2008-01-17

申请人： Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Philip Anthony Marvin

发明人： Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Philip Anthony Marvin

IPC分类号： B32B37/00

CPC分类号： H05K3/0014 ,  H01H2219/01 ,  H05K1/0284 ,  H05K1/185 ,  H05K3/4611 ,  H05K2201/0141 ,  H05K2201/091 ,  H05K2203/1105 ,  H05K2203/302

摘要： A method is for making a non-planar three-dimensional (3D) multilayered circuit board. The method may include forming a stacked arrangement including at least one pair of liquid crystal polymer (LCP) layers with a bonding layer therebetween. The stacked arrangement may further include at least one electrically conductive pattern layer on at least one of the LCP layers. The method may further include heating and applying pressure to the stacked arrangement to shape the stacked arrangement into a non-planar 3D shape and concurrently causing the bonding layer to bond together the adjacent LCP layers of the stacked arrangement to thereby form the non-planar 3D multi-layered circuit board.

摘要翻译： 一种制造非平面三维（3D）多层电路板的方法。 该方法可以包括形成包括至少一对液晶聚合物（LCP）层的层叠布置，其间具有结合层。 所述堆叠布置还可包括至少一个LCP层上的至少一个导电图案层。 该方法还可以包括加热和施加压力到堆叠的布置以将堆叠布置形成非平面3D形状并且同时使结合层将堆叠布置的相邻LCP层结合在一起，从而形成非平面3D 多层电路板。

公开(公告)号：US09117602B2

公开(公告)日：2015-08-25

申请号：US12016089

申请日：2008-01-17

申请人： Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Paul Brian Jaynes ,  Philip Anthony Marvin

发明人： Louis Joseph Rendek, Jr. ,  Lawrence Wayne Shacklette ,  Paul Brian Jaynes ,  Philip Anthony Marvin

IPC分类号： H05K1/03 ,  H05K1/09 ,  H01H13/704 ,  H05K1/02 ,  H05K3/46

CPC分类号： H01H13/704 ,  H01H11/00 ,  H05K1/0284 ,  H05K3/303 ,  H05K3/4614 ,  H05K3/4626 ,  H05K3/4632 ,  H05K2201/0141 ,  H05K2201/091 ,  Y10T29/49107 ,  Y10T29/4913

摘要： An electronic device includes a multilayer circuit board having a non-planar three-dimensional shape defining a membrane switch recess therein. The multilayer circuit board may include at least one liquid crystal polymer (LCP) layer, and at least one electrically conductive pattern layer thereon defining at least one membrane switch electrode adjacent the membrane switch recess to define a membrane switch. The electronic may further include a compressible dielectric material filling the membrane switch recess. The electronic device may also include at least one spring member within the membrane switch recess.

摘要翻译： 电子设备包括具有在其中限定薄膜开关凹部的非平面三维形状的多层电路板。 多层电路板可以包括至少一个液晶聚合物（LCP）层和至少一个导电图案层，其上限定了与薄膜开关凹部相邻的至少一个薄膜开关电极以限定薄膜开关。 电子器件还可以包括填充薄膜开关凹部的可压缩电介质材料。 电子设备还可以包括膜开关凹部内的至少一个弹簧构件。

公开(公告)号：US08384341B2

公开(公告)日：2013-02-26

申请号：US12607472

申请日：2009-10-28

申请人： Lawrence Wayne Shacklette ,  Louis Joseph Rendek, Jr. ,  David M. Smith

发明人： Lawrence Wayne Shacklette ,  Louis Joseph Rendek, Jr. ,  David M. Smith

IPC分类号： H02J7/00 ,  H01M2/14 ,  G06F7/64

CPC分类号： H01M10/465 ,  H01M4/525 ,  H01M4/5825 ,  H01M10/0436 ,  H01M10/0562 ,  H01M10/0585 ,  Y10T29/49108

摘要： A micro electrical-mechanical systems (MEMS) device INCLUDES a MEMS substrate and at least one MEMS structure on the MEMS substrate. In addition, there is at least one battery cell on the MEMS substrate coupled to the at least one MEMS structure. The at least one battery cell includes a support fin extending vertically upward from the MEMS substrate and a first electrode layer on the support fin. In addition, there is an electrolyte layer on the cathode layer, and a second electrode layer on the electrolyte layer. The support fin may have a height greater than a width. The first electrode layer may have a processing temperature associated therewith that exceeds a stability temperature associated with the second electrode layer.

摘要翻译： 微机电系统（MEMS）装置包括MEMS基板和MEMS基板上的至少一个MEMS结构。 此外，在MEMS衬底上存在至少一个耦合到至少一个MEMS结构的电池单元。 所述至少一个电池单元包括从所述MEMS基板垂直向上延伸的支撑翅片和所述支撑翅片上的第一电极层。 此外，阴极层上存在电解质层，电解质层上具有第二电极层。 支撑翅片可以具有高于宽度的高度。 第一电极层可以具有与其相关联的处理温度，其超过与第二电极层相关联的稳定性温度。

公开(公告)号：US08693203B2

公开(公告)日：2014-04-08

申请号：US13007035

申请日：2011-01-14

申请人： Louis Joseph Rendek, Jr. ,  Michael Weatherspoon ,  Casey Philip Rodriguez ,  David Nicol

发明人： Louis Joseph Rendek, Jr. ,  Michael Weatherspoon ,  Casey Philip Rodriguez ,  David Nicol

IPC分类号： H05K1/00

CPC分类号： H01L24/83 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/33 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11422 ,  H01L2224/1148 ,  H01L2224/13021 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0306 ,  H05K3/281 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0141 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49144 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/31721 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00

摘要： A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.

摘要翻译： 制造电子器件的方法包括在刚性晶片衬底上形成互连层堆叠，所述刚性晶片衬底具有多个图案化电导体层，相邻图案化电导体层之间的介电层，以及位于最上图案化电导体层上的至少一个焊盘 。 形成具有与至少一个焊盘对准的至少一个孔的LCP焊接掩模。 将LCP焊接掩模和互连层堆叠对齐并层压在一起。 焊料定位在至少一个孔中。 使用焊料将至少一个电路部件连接到至少一个焊盘。

公开(公告)号：US08472207B2

公开(公告)日：2013-06-25

申请号：US13007072

申请日：2011-01-14

申请人： Louis Joseph Rendek, Jr. ,  Casey Philip Rodriguez ,  Steven R. Snyder

发明人： Louis Joseph Rendek, Jr. ,  Casey Philip Rodriguez ,  Steven R. Snyder

IPC分类号： H05K1/18

CPC分类号： H05K1/186 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/4602 ,  H05K2201/0141 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49155

摘要： An electronic device includes a substrate with a circuit layer thereon that has a solder pad. There is a liquid crystal polymer (LCP) solder mask on the substrate that has an aperture aligned with the solder pad. There is a fused seam between the substrate and the LCP solder mask. Solder is in the aperture, and a circuit component is electrically coupled to the solder pad via the solder. A first dielectric layer stack having a first plurality of dielectric layers is on the LCP solder mask and has an aperture aligned with the solder pad. There is a first LCP outer sealing layer on the first dielectric layer stack, and a second dielectric layer stack having a second plurality of dielectric layers on the substrate on a side thereof opposite the LCP solder mask. Further, there is a second LCP outer sealing layer on the second dielectric layer stack.

摘要翻译： 电子器件包括其上具有电路层的衬底，其具有焊盘。 在基板上有一个液晶聚合物（LCP）焊接掩模，其具有与焊盘对准的孔。 在基板和LCP焊接掩模之间存在熔接。 焊料在孔中，并且电路部件通过焊料电耦合到焊盘。 具有第一多个电介质层的第一介电层堆叠在LCP焊接掩模上，并且具有与焊盘对准的孔。 在第一介电层堆叠上存在第一LCP外密封层，以及第二介电层堆叠，其在与LCP焊接掩模相对的一侧上的衬底上具有第二多个电介质层。 此外，在第二介质层堆叠上存在第二LCP外密封层。

公开(公告)号：US07531273B2

公开(公告)日：2009-05-12

申请号：US10970663

申请日：2004-10-22

申请人： Michael James Wagner ,  Louis Joseph Rendek, Jr. ,  Robert Ellis Doe ,  Dawson W. Cagle

发明人： Michael James Wagner ,  Louis Joseph Rendek, Jr. ,  Robert Ellis Doe ,  Dawson W. Cagle

IPC分类号： H01M4/36 ,  H01M4/58

CPC分类号： H01M4/583 ,  B82Y30/00 ,  H01M4/5835 ,  H01M4/622 ,  H01M10/0525 ,  Y10S977/734 ,  Y10S977/735

摘要： A composition for forming an electrode for a lithium ion secondary battery includes a carbonaceous material combined with a fullerene material including fullerene species having a carbon content of Cn, where n≧100. The composition is heated to a temperature of 100° C. or greater to facilitate reaction and/or diffusion of the fullerene material with the carbonaceous material, and also to remove lower molecular weight (C

摘要翻译： 用于形成锂离子二次电池用电极的组合物包括与包含碳含量为C n的富勒烯种类的富勒烯材料组合的碳质材料，其中n≥100。 将组合物加热至100℃或更高的温度以促进富勒烯材料与碳质材料的反应和/或扩散，并且还从组合物中除去较低分子量（C <100）的富勒烯。 此外，其它提取技术可以与热处理组合使用以选择性地从富勒烯材料中除去富勒烯种类。 该组合物提高了锂离子电池中电极的电化学性能。

公开(公告)号：US08867219B2

公开(公告)日：2014-10-21

申请号：US13006973

申请日：2011-01-14

申请人： Michael Weatherspoon ,  David Nicol ,  Louis Joseph Rendek, Jr.

发明人： Michael Weatherspoon ,  David Nicol ,  Louis Joseph Rendek, Jr.

IPC分类号： H05K1/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/683 ,  H05K1/18 ,  H01L23/00 ,  H05K3/46 ,  H05K3/34

CPC分类号： H01L23/4985 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1511 ,  H01L2924/1579 ,  H05K1/036 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/181 ,  H05K1/189 ,  H05K3/32 ,  H05K3/3436 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4632 ,  H05K3/467 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0141 ,  H05K2201/10674 ,  Y10T29/4913 ,  Y10T29/49224 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method is for making an electronic device and includes forming an interconnect layer stack on a sacrificial substrate and having a plurality of patterned electrical conductor layers, and a dielectric layer between adjacent patterned electrical conductor layers. The method also includes laminating and electrically joining through an intermetallic bond a liquid crystal polymer (LCP) substrate to the interconnect layer stack on a side thereof opposite the sacrificial substrate. The method further includes removing the sacrificial substrate to expose a lowermost patterned electrical conductor layer, and electrically coupling at least one first device to the lowermost patterned electrical conductor layer.

摘要翻译： 一种用于制造电子器件的方法，包括在牺牲衬底上形成互连层堆叠并且具有多个图案化的导电层，以及在相邻的图案化电导体层之间的介电层。 该方法还包括通过液晶聚合物（LCP）衬底的金属间键合层叠和电连接到与牺牲衬底相对的一侧上的互连层堆叠。 该方法还包括去除牺牲衬底以暴露最下图案化电导体层，并将至少一个第一器件电耦合到最下图案化电导体层。