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1.发明申请公开(公告)号：US20100244241A1
公开(公告)日：2010-09-30
申请号：US12412279
申请日：2009-03-26
IPC分类号： H01L23/498 , H01L21/768 , H01L21/50
CPC分类号： H01L21/76898 , H01L21/302 , H01L21/56 , H01L21/561 , H01L21/76885 , H01L23/3114 , H01L23/481 , H01L23/49811 , H01L24/02 , H01L24/04 , H01L24/05 , H01L24/06 , H01L24/10 , H01L24/11 , H01L24/12 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L2224/02166 , H01L2224/02181 , H01L2224/0391 , H01L2224/0401 , H01L2224/05083 , H01L2224/0557 , H01L2224/05572 , H01L2224/06181 , H01L2224/10125 , H01L2224/1184 , H01L2224/11901 , H01L2224/13009 , H01L2224/1301 , H01L2224/13025 , H01L2224/13027 , H01L2224/13082 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/14104 , H01L2224/14181 , H01L2224/16145 , H01L2224/48 , H01L2224/73265 , H01L2225/06513 , H01L2225/06541 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/181 , H01L2924/1815 , H01L2924/182 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2224/13099 , H01L2924/00012 , H01L2924/00 , H01L2224/05552 , H01L2224/11849 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.
摘要翻译： 半导体器件在衬底的第一表面中具有导电通孔。 在衬底的第一表面上形成第一互连结构。 在第一互连结构上形成第一凸点。 第一凸起形成在导电通孔上方或偏离导电通孔。 密封剂沉积在第一凸起和第一互连结构之上。 去除一部分密封剂以露出第一凸块。 去除衬底的第二表面的一部分以暴露导电通孔。 密封剂提供结构支撑，并且在使衬底变薄时不需要单独的载体晶片。 第二互连结构形成在衬底的第二表面上。 在第一凸起上形成第二凸点。 多个半导体器件可以通过导电通孔堆叠并电连接。
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2.发明申请Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief 有权半导体器件和UBM与保形介质层之间形成合适的聚合物层/ RDL用于应力释放的方法公开(公告)号：US20100140752A1
公开(公告)日：2010-06-10
申请号：US12332325
申请日：2008-12-10
IPC分类号： H01L29/40 , H01L21/44 , H01L23/538 , H01L29/41
CPC分类号： H01L23/481 , H01L23/3121 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/29 , H01L24/48 , H01L2224/02126 , H01L2224/02313 , H01L2224/0236 , H01L2224/024 , H01L2224/0401 , H01L2224/04042 , H01L2224/05111 , H01L2224/05155 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/10126 , H01L2224/13022 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/16225 , H01L2224/16235 , H01L2224/29111 , H01L2224/2919 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/4823 , H01L2224/48247 , H01L2224/73265 , H01L2224/83805 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2924/0665 , H01L2224/05552 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion.
摘要翻译： 半导体器件具有形成在衬底的顶表面上的第一导电层。 在衬底上形成第一绝缘层。 第一绝缘层形成在第一绝缘层上。 在第一导电层和第一介电层上形成第二导电层。 第二介电层形成在第二导电层上。 聚合物材料沉积在第二介电层和第二导电层上。 在聚合物材料和第二导电层上形成第三导电层。 第三导电层电连接到第二导电层。 在第三导电层上形成第一焊料凸块。 通过衬底的背面形成导电通孔。 导电通孔电连接到第一导电层。 聚合物材料具有低的热膨胀系数。
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公开(公告)号：US20110101509A1
公开(公告)日：2011-05-05
申请号：US13004111
申请日：2011-01-11
IPC分类号： H01L23/552 , H01L23/48
CPC分类号： H01L23/147 , H01L21/563 , H01L23/49822 , H01L23/552 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/16152 , H01L2924/19107 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer that exposes the conductive layer, a second via formed in the carrier wafer that exposes the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second insulation layers are deposited over the first and second metal layers respectively. The first or second insulation layer has an etched portion to expose a portion of the first or second metal layer.
摘要翻译： 半导体器件具有用于支撑器件的晶片和形成在晶片顶表面上的导电层。 载体晶片永久地接合在导电层上。 在晶片和载体晶片内形成互连结构。 所述互连结构包括形成在所述晶片中的第一通孔，所述第一通孔暴露所述导电层，形成在所述载体晶片中的暴露所述导电层的第二通孔，沉积在所述第一通孔上的第一金属层，所述第一金属层与所述导电层电接触; 导电层和沉积在第二通孔上的第二金属层，第二金属层与导电层电接触。 第一和第二绝缘层分别沉积在第一和第二金属层上。 第一或第二绝缘层具有蚀刻部分以暴露第一或第二金属层的一部分。
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4.发明申请Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias 有权半导体器件和通过硅通孔形成插入器封装的方法公开(公告)号：US20110024916A1
公开(公告)日：2011-02-03
申请号：US12905825
申请日：2010-10-15
CPC分类号： H01L23/3128 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/96 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2223/54426 , H01L2224/0401 , H01L2224/04105 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/12105 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/81005 , H01L2224/82039 , H01L2224/9222 , H01L2224/96 , H01L2225/0651 , H01L2225/06541 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.
摘要翻译： 半导体器件具有用于支撑半导体器件的载体。 第一半导体管芯安装在载体上。 具有第一穿通硅通孔（TSV）的第一虚设裸片安装在载体上。 使用晶片模制材料封装第一半导体管芯和第一个裸管管芯。 载体被移除。 第一再分配层（RDL）形成在第一半导体管芯的第一表面和第一虚设管芯的第一表面上，以电连接第一半导体晶粒管和第一半导体管芯的接触焊盘。 在第一RDL上形成绝缘层。 第二RDL形成在第一虚设裸片的与第一虚设裸片的第一表面相对的第二表面上，并与第一TSV电连接。 半导体封装连接到第二RDL。
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公开(公告)号：US07863721B2
公开(公告)日：2011-01-04
申请号：US12137242
申请日：2008-06-11
IPC分类号： H01L23/02
CPC分类号： H01L23/3114 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/11849 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13118 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/48091 , H01L2224/73265 , H01L2224/9202 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/0001 , H01L2924/00011 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/04941 , H01L2924/10329 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2924/014 , H01L2924/00 , H01L2224/81805 , H01L2924/00012
摘要： A semiconductor device has first and second wafers having bond pads. The bond pad of the second wafer is connected to the bond pad of the first wafer using a conductive adhesive. A first interconnect structure is formed within the second wafer and includes a first via formed in a back surface of the second wafer to expose the bond pad of the second wafer. A first metal layer is formed conformally over the first via and is in electrical contact with the bond pad of the second wafer. A third wafer is mounted over the second wafer by connecting a bond pad formed over a front surface of the third wafer to the first metal layer. A second interconnect structure is formed over a backside of the third wafer opposite the front surface. The second interconnect structure is electrically connected to the first metal layer.
摘要翻译： 半导体器件具有第一和第二晶片，具有接合焊盘。 使用导电粘合剂将第二晶片的接合焊盘连接到第一晶片的焊盘。 第一互连结构形成在第二晶片内，并且包括形成在第二晶片的后表面中的第一通孔，以暴露第二晶片的接合焊盘。 第一金属层在第一通孔上保形地形成并且与第二晶片的接合焊盘电接触。 通过将形成在第三晶片的前表面上的接合焊盘连接到第一金属层，将第三晶片安装在第二晶片上。 在第三晶片的与前表面相对的背面上形成第二互连结构。 第二互连结构电连接到第一金属层。
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6.发明授权Semiconductor device and method of forming an interposer package with through silicon vias 有权半导体器件和通过硅通孔形成插入器封装的方法公开(公告)号：US07838337B2
公开(公告)日：2010-11-23
申请号：US12325587
申请日：2008-12-01
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/96 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2223/54426 , H01L2224/0401 , H01L2224/04105 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/12105 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/81005 , H01L2224/82039 , H01L2224/9222 , H01L2224/96 , H01L2225/0651 , H01L2225/06541 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device is fabricated by providing a carrier for supporting the semiconductor device. A first semiconductor die is mounted to the carrier. The first semiconductor die has a contact pad. A first dummy die is mounted to the carrier. The first dummy die has a through-silicon via (TSV). The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. A first interconnect structure is formed over the first semiconductor die and the first dummy die. The first interconnect structure is connected to the contact pad of the first semiconductor die and the TSV of the first dummy die. The carrier is removed and a second interconnect structure is formed over the first semiconductor die and the first dummy die. The second interconnect structure is connected to the TSV of the first dummy die. A semiconductor package is connected to the second interconnect structure.
摘要翻译： 通过提供用于支撑半导体器件的载体来制造半导体器件。 第一半导体管芯安装到载体上。 第一半导体管芯具有接触焊盘。 第一个虚设裸片安装在载体上。 第一个虚设裸片具有穿硅通孔（TSV）。 使用晶片模制材料封装第一半导体管芯和第一个裸管管芯。 第一互连结构形成在第一半导体管芯和第一虚设裸片上。 第一互连结构连接到第一半导体管芯的接触焊盘和第一虚设管芯的TSV。 移除载体，在第一半导体管芯和第一虚设管芯上形成第二互连结构。 第二互连结构连接到第一虚设裸片的TSV。 半导体封装连接到第二互连结构。
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公开(公告)号：US20090243083A1
公开(公告)日：2009-10-01
申请号：US12055171
申请日：2008-03-25
CPC分类号： H01L23/147 , H01L21/563 , H01L23/49822 , H01L23/552 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15311 , H01L2924/16152 , H01L2924/19107 , H01L2924/3025 , H01L2224/05599
摘要： A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer.
摘要翻译： 半导体器件具有用于支撑器件的晶片和形成在晶片顶表面上的导电层。 载体晶片永久地接合在导电层上。 在晶片和载体晶片内形成互连结构。 所述互连结构包括形成在所述晶片中的暴露所述导电层的第一通孔，暴露所述导电层的所述载体晶片中形成的第二通孔，沉积在所述第一通孔上的第一金属层，所述第一金属层与所述导电层电接触 以及沉积在所述第二通孔上的第二金属层，所述第二金属层与所述导电层电接触。 第一和第二钝化层沉积在第一和第二金属层上。 第一钝化层或第二钝化层具有蚀刻部分以暴露第一金属层或第二金属层的一部分。
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8.发明授权Semiconductor device and method of forming an interconnect structure for 3-D devices using encapsulant for structural support 有权用于使用用于结构支撑的密封剂的3-D器件的互连结构的半导体器件和方法公开(公告)号：US09029193B2
公开(公告)日：2015-05-12
申请号：US12775170
申请日：2010-05-06
IPC分类号： H01L21/44 , H01L23/31 , H01L21/48 , H01L21/56 , H01L23/538 , H01L25/065 , H01L25/00
CPC分类号： H01L23/3128 , H01L21/486 , H01L21/561 , H01L23/3121 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H01L25/50 , H01L2224/16238 , H01L2224/73265 , H01L2224/81385 , H01L2924/01004 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/13091 , H01L2924/1433 , H01L2924/19041
摘要： A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
摘要翻译： 半导体器件具有形成在衬底的第一侧上的第一互连结构。 半导体管芯安装到第一互连结构。 密封剂沉积在半导体管芯和第一互连结构上用于结构支撑。 衬底的与衬底的第一侧相对的第二侧的一部分被去除以减小其厚度。 密封剂在稀化过程中保持基材的坚固性。 TSV通过衬底的第二侧形成到第一互连结构。 在TSV中形成第二互连结构。 TSV具有形成在衬底的第二侧上的第一绝缘层和形成在第一绝缘层上并进入TSV的第一导电层。 第二互连结构具有在远离TSV的区域中形成在第一导电层之上的第二导电层。
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9.发明授权Semiconductor device and method of forming an interposer package with through silicon vias 有权半导体器件和通过硅通孔形成插入器封装的方法公开(公告)号：US08263439B2
公开(公告)日：2012-09-11
申请号：US12905825
申请日：2010-10-15
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/565 , H01L21/568 , H01L21/6835 , H01L23/481 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/544 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/48 , H01L24/73 , H01L24/96 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L2223/54426 , H01L2224/0401 , H01L2224/04105 , H01L2224/05111 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/12105 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13118 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/16237 , H01L2224/24137 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/73259 , H01L2224/73265 , H01L2224/81005 , H01L2224/82039 , H01L2224/9222 , H01L2224/96 , H01L2225/0651 , H01L2225/06541 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device has a carrier for supporting the semiconductor device. A first semiconductor die is mounted over the carrier. A first dummy die having a first through-silicon via (TSV) is mounted over the carrier. The first semiconductor die and the first dummy die are encapsulated using a wafer molding material. The carrier is removed. A first redistribution layer (RDL) is formed over a first surface of the first semiconductor die and a first surface of the first dummy die to electrically connect the first TSV and a contact pad of the first semiconductor die. An insulation layer is formed over the first RDL. A second RDL is formed over a second surface of the first dummy die opposite the first surface of the first dummy die and electrically connected to the first TSV. A semiconductor package is connected to the second RDL.
摘要翻译： 半导体器件具有用于支撑半导体器件的载体。 第一半导体管芯安装在载体上。 具有第一穿通硅通孔（TSV）的第一虚设裸片安装在载体上。 使用晶片模制材料封装第一半导体管芯和第一个裸管管芯。 载体被移除。 第一再分配层（RDL）形成在第一半导体管芯的第一表面和第一虚设管芯的第一表面上，以电连接第一半导体晶粒管和第一半导体管芯的接触焊盘。 在第一RDL上形成绝缘层。 第二RDL形成在第一虚设裸片的与第一虚设裸片的第一表面相对的第二表面上，并与第一TSV电连接。 半导体封装连接到第二RDL。
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10.发明申请Semiconductor Device and Method of Forming an Interconnect Structure for 3-D Devices Using Encapsulant for Structural Support 有权半导体器件和使用用于结构支持的封装剂的3-D器件互连结构的方法公开(公告)号：US20100213610A1
公开(公告)日：2010-08-26
申请号：US12775188
申请日：2010-05-06
IPC分类号： H01L23/498
CPC分类号： H01L23/3128 , H01L21/486 , H01L21/561 , H01L23/3121 , H01L23/5384 , H01L23/5385 , H01L25/0655 , H01L25/50 , H01L2224/16238 , H01L2224/73265 , H01L2224/81385 , H01L2924/01004 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/13091 , H01L2924/1433 , H01L2924/19041
摘要： A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
摘要翻译： 半导体器件具有形成在衬底的第一侧上的第一互连结构。 半导体管芯安装到第一互连结构。 密封剂沉积在半导体管芯和第一互连结构上用于结构支撑。 衬底的与衬底的第一侧相对的第二侧的一部分被去除以减小其厚度。 密封剂在稀化过程中保持基材的坚固性。 TSV通过衬底的第二侧形成到第一互连结构。 在TSV中形成第二互连结构。 TSV具有形成在衬底的第二侧上的第一绝缘层和形成在第一绝缘层上并进入TSV的第一导电层。 第二互连结构具有在远离TSV的区域中形成在第一导电层之上的第二导电层。
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