摘要:
A wiring substrate manufacturing method includes: preparing a wiring substrate including a core layer having a principal surface, a resin insulating layer and a conductor layer alternately laminated to form at least one laminated layer on the one principal surface of the core layer, a solder resist layer including opening portions and formed on an outermost surface of the at least one laminated layer such that respective portions of an outermost conductor layer are exposed from the opening portions; forming a Sn-containing underlying layer on the respective portions of the outermost conductor layer by a plating process; and fusing the Sn-containing underlying layer to the respective portions of the outermost conductor layer by a heating process, then mounting solder balls directly on respective portions of the Sn-containing underlying layer, and then connecting the solder balls to the respective portions of the Sn-containing underlying layers.
摘要:
A method for manufacturing a wiring board for mounting an electronic component, a wiring board for mounting an electronic component, and a method for manufacturing an electronic-component-mounted wiring board are provided. A bonding material paste, which can include solder and an electric insulation material made of a resin, can be placed on chip mount terminal pads and heated to fuse the solder and soften the electric insulation material. Subsequently, the solder is solidified to form solder bumps. Further, the electric insulation material is cured on a surface of each of the solder bumps and a surface of a multilayer board around each of the solder bumps to form an electric insulation surface layer. Accordingly, when a chip is mounted to such wiring boards, the electric insulation surface layer minimizes or eliminates the connection between adjacent solder bumps during re-fusing of the solder.
摘要:
A wiring board has a wiring board main body, a solder resist and solder bumps. The solder resist is formed on a top surface of the wiring board main body, and includes first openings, and second openings that have a diameter larger than that of the first openings. The solder bumps are disposed in the first openings and in the second openings. In addition, top portions of the solder bumps disposed in the first openings have a flat face, while top portions of the solder bumps disposed in the second openings have a non-flat face.
摘要:
A method for manufacturing a wiring board which can simplify a manufacturing step. In a preparation step, a core board and an electronic component are prepared. In an insulating layer formation and fixing step, after accommodating the electronic component in an accommodation hole, a lowermost resin insulating layer is formed, and a gap between the electronic component and the core board is filled with a part of the lowermost resin insulating layer so as to fix the electronic component to the core board. In an opening portion formation step, a portion of the lowermost resin insulating layer located directly above the gap between the electronic component and the core board is removed so as to form an opening portion exposing a part of a core board main surface side conductor and a component main surface side electrode. In a main surface side connecting conductor formation step, a main surface side connecting conductor is formed in the opening portion so as to connect the core board main surface side conductor to the component main surface side electrode.
摘要:
A process for manufacturing a wiring substrate, comprising: a step of forming an insulating resin layer containing an inorganic filler over a wiring layer formed on at least one surface of an insulating substrate; a step of forming a thin copper film layer by roughening a surface of the insulating resin layer and plating the same electrolessly with copper; a step of forming an insulating film over the thin copper film layer; a step of forming plated resists profiling a pattern by exposing and developing the insulating film with the pattern; and a step of forming wiring pattern layers by an electrolytic copper plating on a surface of the insulating resin layer having the plated resists formed thereon, wherein at least one of the plated resists has a width of less than 20 μm, and the plated resists include adjoining plated resists in which a clearance between said adjoining plated resists has a width of less than 20 μm.
摘要:
A pin standing resin substrate including a resin substrate having a substantially plate-shaped main surface and composed of one of a resin and a composite material containing a resin, and having a pin-pad exposed from the main surface; and a pin soldered to the pin-pad, wherein the pin has been thermally treated by heating so as to soften the pin. The pin has a rod-like portion composed of a copper base metal and an enlarged diameter portion made of the same material as the rod-like portion. The enlarged diameter portion has a larger diameter than the rod-like portion and is formed at one end of the rod-like portion. At least the enlarged diameter portion is soldered to the pin-pad. Also disclosed is a method of making the pin standing resin substrate, a pin for bonding with the resin substrate, and a method of making the pin.
摘要:
A wiring board and a method for manufacturing the wiring board reinforced by means of a resin is provided. Embodiments of the wiring board allow for reliable attachment of a connection member, like a socket, to a terminal member. For example, a base of terminal pins is put on pin grid array (PGA) terminal pads, and a bonding material paste including solder and an electric insulation material made of a resin is placed on each of the PGA terminal pads. The bonding material paste is then heated to fuse the solder and soften the electric insulation material. Subsequently, the bonding material paste is cooled to solidify the solder and bond each of the bases to a corresponding PGA terminal pad and form an electric insulation surface layer on an exposed surface of each of solder junctions to which the respective bases are bonded.
摘要:
A multilayer wiring board including a build-up layer, formed from one or more conductor and resin insulation layers that are layered one on top of the other, having conductive pads formed on a surface of at least one resin insulation layer so as to project from the surface are provided. The conductive pads may each include a columnar portion situated at a lower part thereof and a convex portion situated at a higher part thereof, wherein a surface of the convex portion may assume a continual curved shape. A solder layer may be formed over an upper surface of the conductive pads. Certain embodiments make it possible to minimize or eliminate the concentration of stress on the conductive pads, and may inhibit the occurrence of defective connections to a semiconductor element and infliction of damage to the conductive pads.
摘要:
Disclosed is a method of manufacturing a multilayer wiring substrate having a principal plane of the substrate and a rear plane thereof, having a structure such that a plurality of resin insulating layers and a plurality of conductor layers are laminated, and a plurality of chip component connecting terminals to which chip components are connectable are disposed on the principal plane of the substrate. This method has a feature including a plating layer forming process in which product plating layers which provide the plurality of chip component connecting terminals and a dummy plating layer on the surrounding of the product plating layers are formed on the surface of an exposed outermost resin insulating layer at the principal plane of the substrate. This method permits a thickness dispersion of the chip component connecting terminals to be suppressed and permits a connection reliability thereof to the chip components to be increased.
摘要:
An electronic device comprised of a wiring board with a semiconductor component. The device is unlikely to have any defects, such as cracks to a solder joint portion during a reflow process of a flip-chip connection. The semiconductor component is flip-chip bonded at a pad array at a component side thereof to a pad array at a board side by way of an individual solder joint portion. In a solder resist layer at a semiconductor component side and a solder resist layer at a board side, D/D0 is prepared to be in a range of 0.70 to 0.99, where D is a bottom inner diameter of an opening at the board side and D0 is a bottom inner diameter of an opening at the component side.