公开(公告)号：US06703705B2

公开(公告)日：2004-03-09

申请号：US09996054

申请日：2001-11-28

申请人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

发明人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC分类号： H01L2352

CPC分类号： H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

摘要翻译： 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US06949815B2

公开(公告)日：2005-09-27

申请号：US10746603

申请日：2003-12-23

申请人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

发明人： Takao Yamazaki ,  Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi ,  Yuzo Shimada

IPC分类号： H05K3/34 ,  H01L21/60 ,  H01L21/822 ,  H01L23/12 ,  H01L23/50 ,  H01L23/64 ,  H01L27/04 ,  H01L23/52 ,  H01L23/32 ,  H01L23/48 ,  H01G9/05

CPC分类号： H01L24/81 ,  H01L23/50 ,  H01L23/642 ,  H01L24/73 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

摘要翻译： 半导体器件具有在电路形成面的周边部分设置有多个电源线连接焊盘和接地线连接焊盘的LSI器件，电连接到每个焊盘并粘附到LSI的金属箔引线5 通过绝缘层的器件，以及安装在金属箔引线的一个表面上的去耦电容器。

公开(公告)号：US06818469B2

公开(公告)日：2004-11-16

申请号：US10445330

申请日：2003-05-27

申请人： Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi

发明人： Toru Mori ,  Akinobu Shibuya ,  Shintaro Yamamichi

IPC分类号： H01L2100

CPC分类号： H05K1/162 ,  H01L2224/04105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/0317 ,  H05K2201/09509

摘要： A thin film capacitor is provided with a substrate having a thickness equal to or more than 2 &mgr;m and equal to or less than 100 &mgr;m; a lower electrode on the substrate, which includes at least a highly elastic electrode and an anti-oxidation electrode on the highly elastic electrode; a dielectric thin film on the first lower electrode; and an upper electrode on the dielectric thin film; wherein the highly elastic electrode is made of a material having a Young's modulus higher than that of the anti-oxidation electrode.

摘要翻译： 薄膜电容器具有厚度等于或大于2μm且等于或小于100μm的基板; 所述基板上的下部电极，在所述高弹性电极上至少包括高弹性电极和抗氧化电极; 第一下电极上的电介质薄膜; 和电介质薄膜上的上电极; 其中所述高弹性电极由杨氏模量高于所述抗氧化电极的杨氏模量的材料制成。

公开(公告)号：US06524905B2

公开(公告)日：2003-02-25

申请号：US09903316

申请日：2001-07-11

申请人： Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

发明人： Shintaro Yamamichi ,  Toru Mori ,  Akinobu Shibuya ,  Takao Yamazaki ,  Yuzo Shimada

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L27/0688 ,  H01L2221/68363 ,  H01L2224/04042 ,  H01L2224/4847 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00

摘要： A semiconductor device provided with a thin film capacitor having a small equivalent series inductance is provided, which can be operated at a high frequency range and contributes to size reduction of the electronic devices. The semiconductor device comprises a device formed on a silicon substrate 1a, interlayer insulating films 3a, 3b, and 3c, wiring blocks including a power source wire block and a ground wire block, and a thin film capacitor 14 formed on an uppermost insulating layer. The thin film capacitor 14 comprises a lower electrode 6 connected to the ground wire block 4e through a contact 5d, an upper electrode 8 which is connected to the power source wire block 4d through a contact 5d, and which extends above the lower electrode 6, and a dielectric layer 7 which is inserted between the lower and the upper electrodes.

摘要翻译： 提供了具有小等效串联电感的薄膜电容器的半导体器件，其可以在高频范围下操作并且有助于电子器件的尺寸减小。 半导体器件包括形成在硅衬底1a，层间绝缘膜3a，3b和3c上的器件，包括电源线块和接地线块的布线块，以及形成在最上层绝缘层上的薄膜电容器14。 薄膜电容器14包括通过接触件5d连接到接地线块4e的下电极6，通过接触件5d连接到电源线块4d并且在下电极6上方延伸的上电极8， 以及插入在下电极和上电极之间的电介质层7。

公开(公告)号：US06515324B2

公开(公告)日：2003-02-04

申请号：US09942817

申请日：2001-08-30

申请人： Akinobu Shibuya ,  Shintaro Yamamichi ,  Toru Mori ,  Takao Yamazaki ,  Yuzo Shimada

发明人： Akinobu Shibuya ,  Shintaro Yamamichi ,  Toru Mori ,  Takao Yamazaki ,  Yuzo Shimada

IPC分类号： H01L27178

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H01L2924/00

摘要： A capacitor has a lower electrode, a dielectric thin film, an upper electrode, and an insulation cover layer formed on an insulation substrate made of an organic film or a ceramic material, and through holes formed at positions corresponding to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package, with electrodes for connection to input and output pads of a semiconductor element or to input and output terminals of a semiconductor package provided within through holes. In a method for mounting the capacitor, the capacitor is interposed between a flip-chip connected semiconductor element and a mounting substrate.

公开(公告)号：US08815678B2

公开(公告)日：2014-08-26

申请号：US11928460

申请日：2007-10-30

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L21/8242 ,  H01L21/316 ,  H01L49/02 ,  C23C16/455 ,  G11C11/404 ,  H01L21/314 ,  H01L27/108 ,  C23C16/40

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US08212299B2

公开(公告)日：2012-07-03

申请号：US10170813

申请日：2002-06-13

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1−x)O2(0

摘要翻译： 在薄膜晶体管中，上部电极和下部电极中的每一个由选自由TiN，Ti，W，WN，Pt，Ir，Ru所示的金属和金属氮化物组成的组中的至少一种形成 。 电容器电介质膜由选自ZrO 2，HfO 2，（Zr x，Hf 1-x）O 2（0

公开(公告)号：US20120119338A1

公开(公告)日：2012-05-17

申请号：US13200944

申请日：2011-10-05

申请人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

发明人： Takahito Watanabe ,  Shintaro Yamamichi ,  Yoshitaka Ushiyama

IPC分类号： H01L23/552 ,  H01L21/02

CPC分类号： H01L23/58 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/552 ,  H01L24/05 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/97 ,  H01L27/224 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2916 ,  H01L2224/2919 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/1435 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

摘要翻译： 半导体芯片包括磁存储装置，并且在第一面上包括电极焊盘。 至少在电极焊盘露出的状态下，半导体芯片被覆有磁屏蔽层。 半导体芯片通过凸块安装在互连基板上。 半导体芯片和互连基板中的至少一个包括凸部，并且凸块设置在凸部上。

公开(公告)号：US08169013B2

公开(公告)日：2012-05-01

申请号：US11637147

申请日：2006-12-12

申请人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

发明人： Toshihiro Iizuka ,  Tomoe Yamamoto ,  Mami Toda ,  Shintaro Yamamichi

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L27/108 ,  C23C16/405 ,  C23C16/45525 ,  G11C11/404 ,  G11C2207/104 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/55 ,  H01L28/60 ,  H01L28/65 ,  H01L28/90

摘要： A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0

摘要翻译： 一种具有形成在同一半导体芯片上的逻辑部分和存储部分的半导体器件，包括：形成在逻辑部分中并具有栅电极和源极和漏极区域的第一晶体管，以及形成在存储部分中的第二晶体管， 栅极电极，源极和漏极区域以及电容器，电容器是MIM结构，并且具有夹在其间的上部和下部金属电极和电容器电介质膜，所述电容器电介质膜由介电材料形成，所述绝缘材料选自 由ZrO2，Hf92，（Zrx，Hf1-x）O2（0

公开(公告)号：US08039756B2

公开(公告)日：2011-10-18

申请号：US11542309

申请日：2006-10-04

申请人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

发明人： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC分类号： H05K1/16

CPC分类号： H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/32 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K3/0023 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

摘要： A multilayered wiring board has electrodes disposed on a first surface and a second surface, alternately layered insulation layers and wiring layers, and vias that are disposed in the insulation layer and electrically connect the wiring layers. The second electrode disposed on the second surface is embedded in the insulation layer exposed on said second surface, and the second wiring layer covered by the insulation layer exposed on said second surface does not have a layer for improving adhesion to the insulation layer.

摘要翻译： 多层布线基板具有设置在第一表面和第二表面上的电极，交替层叠的绝缘层和布线层以及布置在绝缘层中并且电连接布线层的通孔。 设置在第二表面上的第二电极嵌入在暴露在所述第二表面上的绝缘层中，并且由暴露在所述第二表面上的绝缘层覆盖的第二布线层不具有用于改善与绝缘层的粘附性的层。