公开(公告)号：US20040182714A1

公开(公告)日：2004-09-23

申请号：US10767697

申请日：2004-01-29

申请人： Nikko Materials Co., Ltd.

发明人： Toru Imori ,  Masashi Kumagai ,  Junnosuke Sekiguchi

IPC分类号： C25D005/02 ,  H01L021/288 ,  H05K003/00 ,  H01L021/44 ,  H01L021/445

CPC分类号： C23C18/30 ,  C23C18/1879

摘要： Resin cloths, powders, specular bodies and other objects resistant to conventional plating can be plated with metals by a simple method. According to the metal plating method of the present invention, electroless plating is performed after the surface of a object to be plated is treated with a pretreatment agent obtained by reacting or mixing in advance a noble metal compound (catalyst) with a silane-coupling agent having functional groups capable of capturing metals. According to this method, metal plating can be securely applied to powders, resin cloths, semiconductor wafers, and other specular bodies. Moreover, the problem of the insufficient coverage of the seed layer on the inside walls of vias and trenches during the formation of fine wiring can be addressed by applying this method to semiconductor wafers. The silane-coupling agent may be a compound containing azole groups, preferably an imidazole.

摘要翻译： 树脂布，粉末，镜面物体和其他耐常规镀层的物体可用简单的方法镀金属。 根据本发明的金属镀覆方法，在将待镀镀物体的表面用预先将贵金属化合物（催化剂）与硅烷偶联剂进行反应或混合而获得的预处理剂进行处理之后进行化学镀 具有能够捕获金属的官能团。 根据该方法，可以将金属电镀牢固地施加到粉末，树脂布，半导体晶片和其它镜面体上。 此外，通过将该方法应用于半导体晶片，可以解决在形成精细布线期间通孔和沟槽的内壁上种子层覆盖不足的问题。 硅烷偶联剂可以是含有唑类，优选咪唑的化合物。

公开(公告)号：US20020195347A1

公开(公告)日：2002-12-26

申请号：US10218810

申请日：2002-08-14

发明人： Cindy Reidsema Simpson ,  Matthew T. Herrick ,  Gregory S. Etherington ,  James Derek Legg

IPC分类号： C25B009/00 ,  C25B015/00 ,  C25C007/00 ,  C25D003/12 ,  C25D003/38 ,  C25D003/48 ,  C25D005/02 ,  C25D017/00 ,  H01L021/288 ,  H01L021/445

CPC分类号： H01L21/2885 ,  C25D3/665 ,  C25D5/00 ,  C25D5/04 ,  C25D5/18 ,  C25D7/123 ,  C25D17/001 ,  C25D17/008 ,  C25D21/00 ,  Y10S204/07

摘要： An electroplating system (30) and process makes electrical current density across a semiconductor device substrate (20) surface more uniform during plating to allow for a more uniform or tailored deposition of a conductive material. The electrical current density modifiers (364 and 37) reduce the electrical current density near the edge of the substrate (20). By reducing the current density near the edge of the substrate (20), the plating becomes more uniform or can be tailored so that slightly more material is plated near the center of the substrate (20). The system can also be modified so that the material that electrical current density modifier portions (364) on structures (36) can be removed without having to disassemble any portion of the head (35) or otherwise remove the structures (36) from the system. This in-situ cleaning reduces the amount of equipment downtime, increases equipment lifetime, and reduces particle counts.

摘要翻译： 电镀系统（30）和工艺使得在电镀期间半导体器件衬底（20）表面上的电流密度更均匀，以允许更均匀或定制的导电材料沉积。 电流密度调节剂（364和37）降低了衬底（20）边缘附近的电流密度。 通过降低衬底（20）边缘附近的电流密度，电镀变得更均匀或可以被调整，使得在衬底（20）的中心附近有更多的材料被镀敷。 该系统也可以被修改，使得可以去除结构（36）上的电流密度调节部分（364）的材料，而不必拆卸头部（35）的任何部分或以其他方式从系统中移除结构（36） 。 这种原位清洗可减少设备停机时间，增加设备使用寿命，并减少颗粒数量。

公开(公告)号：US20020134684A1

公开(公告)日：2002-09-26

申请号：US10001683

申请日：2001-10-25

申请人： Shipley Company, L.L.C.

发明人： Jeffrey M. Calvert ,  Denis Morrissey ,  David Merricks

IPC分类号： C25D005/02 ,  H01L021/288 ,  H01L021/445

CPC分类号： H01L21/76861 ,  C25D7/123 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76868 ,  H01L21/76873 ,  H01L2221/1089 ,  H05K3/423

摘要： Disclosed is a process flows for treating seed layers including copper such that various problems such as oxidation and insufficient coverage can be repaired in an effective and efficient manner.

摘要翻译： 公开了用于处理包括铜的种子层的工艺流程，从而可以以有效和有效的方式修复诸如氧化和不充分覆盖的各种问题。

公开(公告)号：US20040118693A1

公开(公告)日：2004-06-24

申请号：US10731907

申请日：2003-12-08

发明人： Gonzalo Amador ,  Roger J. Stierman

IPC分类号： C25D005/02 ,  H01L021/288 ,  H05K003/00 ,  H01L021/445 ,  H01L021/20

CPC分类号： H01L21/288 ,  C23C18/1619 ,  C23C18/1669 ,  H01L24/02 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

摘要： A method and an apparatus for uniform electroless plating of layers onto exposed metallizations in integrated circuits such as bond pads. The apparatus provides means for holding a plurality of wafers, and rotating each wafer at constant speed and synchronous within the plurality. Immersed in a plating solution flowing in substantially laminar motion and at constant speed, the method creates periodic superposition of directions and speeds of the motion of the wafers and the motion of the plating solution. The invention creates periodically changing wafer portions where the directions and speeds are additive and where the directions and speeds are opposed and subtractive. Consequently, highly uniformly layers are electrolessly plated onto the exposed metallizations of bond pads. If the plated layers are bondable metals, the process transforms otherwise unbondable pad metallization into bondable pads.

摘要翻译： 一种用于在诸如接合焊盘的集成电路中的均匀化学镀电镀到暴露的金属化的方法和装置。 该装置提供用于保持多个晶片的装置，并且在多个晶片内以恒定速度和同步旋转每个晶片。 浸入基本层流运动和恒定速度流动的镀液中，该方法产生晶片的运动方向和速度以及电镀液的运动的周期性重叠。 本发明创造周期性变化的晶片部分，其中方向和速度是相加的，并且其方向和速度是相反的和减法的。 因此，高度均匀的层被无电镀在接合焊盘的暴露的金属化上。 如果镀层是可结合的金属，则该工艺将其它不可焊接的焊盘金属化转变成可粘合的焊盘。

公开(公告)号：US20020033342A1

公开(公告)日：2002-03-21

申请号：US09905335

申请日：2001-07-13

发明人： Cyprian Emeka Uzoh ,  Homayoun Talieh ,  Bulent Basol

IPC分类号： C25D005/02 ,  H01L021/288 ,  H01L021/445 ,  C25D005/06 ,  C25D005/34 ,  C25D005/52

CPC分类号： C25D5/00 ,  C23C18/1608 ,  C23C18/165 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1696 ,  C23C18/1848 ,  C23C18/31 ,  C25D5/02 ,  C25D5/10 ,  C25D5/22 ,  C25D5/34 ,  H01L21/2885 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L24/11 ,  H01L2221/1089 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01057 ,  H01L2924/0106 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/3011

摘要： The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.

摘要翻译： 本发明涉及一种制造高性能芯片互连和封装的方法，该方法通过提供以更高效和省时的方式在衬底的空腔中沉积导电材料的方法。 这是通过从衬底的顶表面选择性地去除种子层的部分，然后在衬底的空腔中沉积导电材料，其中种子层的部分保留在空腔中。 另一种方法包括在衬底的顶表面上形成氧化物层，使得导电材料可以沉积在空腔中，而不会在衬底的顶表面上形成材料。 本发明还公开了用于形成多级互连的方法和相应的结构。

公开(公告)号：US20020022371A1

公开(公告)日：2002-02-21

申请号：US09760181

申请日：2001-01-12

发明人： Leonard Forbes ,  Kie Y. Ahn

IPC分类号： H01L021/288 ,  H01L021/463

CPC分类号： H01L21/02164 ,  H01L21/02203 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/7682 ,  H01L2221/1047 ,  Y10S438/96

摘要： The invention encompasses methods of forming insulating materials proximate conductive elements. In one aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) chemical vapor depositing a first material proximate a substrate; b) forming cavities within the first material; and c) after forming cavities within the first material, transforming at least some of the first material into an insulative second material. In anther aspect, the invention includes a method of forming an insulating material proximate a substrate comprising: a) forming porous polysilicon proximate a substrate; and b) transforming at least some of the porous polysilicon into porous silicon dioxide. In yet another aspect, the invention includes a method of forming an insulating material between components of an integrated circuit comprising: a) chemical vapor depositing polysilicon between two components; b) electrochemical anodization of the polysilicon to convert the polysilicon into a porous mass having a first volume, the first volume comprising a polysilicon volume and a cavity volume, the cavity volume comprising greater than or equal to about 75% of said first volume; and c) oxidizing the porous polysilicon mass to transform the polysilicon into porous silicon dioxide having a second volume, the second volume comprising a silicon dioxide volume and a cavity volume, the cavity volume comprising less than or equal to about 50% of said second volume.

摘要翻译： 本发明包括在导电元件附近形成绝缘材料的方法。 一方面，本发明包括一种在衬底附近形成绝缘材料的方法，包括：a）化学气相沉积靠近衬底的第一材料; b）在第一材料内形成空腔; 以及c）在所述第一材料中形成空腔之后，将所述第一材料中的至少一些转化为绝缘的第二材料。 在另一方面，本发明包括一种在衬底附近形成绝缘材料的方法，包括：a）在衬底附近形成多孔多晶硅; 和b）将多孔多晶硅中的至少一些转化为多孔二氧化硅。 在另一方面，本发明包括在集成电路的部件之间形成绝缘材料的方法，包括：a）在两个部件之间化学气相沉积多晶硅; b）多晶硅的电化学阳极氧化以将多晶硅转化为具有第一体积的多孔质量体，所述第一体积包含多晶硅体积和腔体积，所述空腔体积包含大于或等于所述第一体积的约75％; 以及c）氧化所述多孔多晶硅质量以将所述多晶硅转化为具有第二体积的多孔二氧化硅，所述第二体积包含二氧化硅体积和空腔体积，所述空腔体积包含小于或等于所述第二体积的约50％ 。

公开(公告)号：US20020000383A1

公开(公告)日：2002-01-03

申请号：US09223472

申请日：1998-12-30

发明人： KEVIN J. LEE

IPC分类号： C25D021/00 ,  C25D005/08 ,  B23H011/00 ,  C25D017/00 ,  H01L021/288 ,  H01L021/445

CPC分类号： H01L21/2885 ,  C25D5/08 ,  C25D7/12 ,  C25D17/001

摘要： The invention discloses a method of electroplating a material onto a semiconductor substrate. A substrate is placed in a cylindrical processing chamber enclosure. A nozzle for spraying a liquid electroplating solution opposes the top surface of the substrate. The electroplating solution flows through the nozzle and outward angularly from the tip of the nozzle, so that the solution flows rotationally on the surface of the substrate.

摘要翻译： 本发明公开了一种将材料电镀到半导体衬底上的方法。 将衬底放置在圆柱形处理室外壳中。 用于喷射液体电镀溶液的喷嘴与基板的顶表面相对。 电镀溶液流过喷嘴并从喷嘴的尖端成角度地向外流动，使得溶液在衬底的表面上旋转地流动。

公开(公告)号：US20040067447A1

公开(公告)日：2004-04-08

申请号：US10451913

申请日：2003-11-14

发明人： Robert Cassat ,  Vincent Lorentz

IPC分类号： G03F007/16 ,  C25D005/02 ,  H01L021/288 ,  G03F007/20 ,  H05K001/11 ,  H01R012/04 ,  G03F007/40 ,  H01L021/445 ,  H05K003/00

CPC分类号： H05K3/4661 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/184 ,  H05K2201/0236 ,  H05K2203/073 ,  H05K2203/1157 ,  H05K2203/125

摘要： The invention concerns a method for making an multilevel interconnection circuitry comprising conductor tracks and micro-vias. The method for producing at least one of the levels comprises the following steps: a) on a substrate including at its surface metallizable and/or potentially metallizable parts (102), forming a first insulating photosensitive resin layer (103) comprising a compound capable of inducing subsequent metallization; b) exposing and revealing the first layer (103) so as to selectively uncover the metallizable and/or potentially metallizable parts (102) of the substrate; c) forming, by metallization, metal conductor tracks (111) and micro-vias (110) at the surface of the first insulating photosensitive resin layer (113) and of the parts uncovered during step b), by providing a second photosensitive resin layer (105) forming a selective protection, the second photosensitive resin layer (105) being eliminated.

摘要翻译： 本发明涉及一种用于制造包括导体轨道和微通孔的多层互连电路的方法。 用于生产至少一个级别的方法包括以下步骤：a）在其表面上包括可金属化和/或潜在可金属化部分（102）的基板上，形成第一绝缘光敏树脂层（103），其包含能够 诱导随后的金属化; b）暴露和露出第一层（103），以便选择性地露出衬底的可镀金属化和/或潜在可金属化部分（102）; c）通过金属化形成在第一绝缘感光性树脂层（113）的表面处的金属导体轨迹（111）和微通孔（110）以及在步骤b）期间未覆盖的部分，通过提供第二感光性树脂层 （105）形成选择性保护，所述第二感光性树脂层（105）被去除。

公开(公告)号：US20040056357A1

公开(公告)日：2004-03-25

申请号：US10632623

申请日：2003-08-01

发明人： Kouji Takahashi ,  Kazuhisa Kusano ,  Noriaki Sakamoto

IPC分类号： C25D005/02 ,  H01L021/288

CPC分类号： H01L24/83 ,  C25D7/12 ,  H01L21/4832 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/498 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05647 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2224/83205 ,  H01L2924/00012

摘要： The overflow of a brazing material (19) from a die pad (11) is prevented by forming a second plating film (14B) on the surface of the die pad (11). The second plating film (14B) is provided around the surface of the die pad 11 so as to enclose an area where a semiconductor element (13) is mounted. In a step of mounting the semiconductor element (13) on the die pad (11) with the brazing material (19), the brazing material (19) overflows from the first plating film (14A) when the semiconductor element (13) is mounted on the upper part of the molten brazing material. However, the second plating film (14B) functions as a blocking area by which the overflow of the brazing material is prevented. Therefore, a short circuit can be prevented from arising between the die pad (11) and the bonding pad (12) because of the brazing material that has spread.

摘要翻译： 通过在管芯焊盘（11）的表面上形成第二镀膜（14B）来防止钎焊材料（19）从管芯焊盘（11）溢出。 第二镀膜（14B）设置在管芯焊盘11的表面周围，以包围安装半导体元件（13）的区域。 在利用钎料（19）将半导体元件（13）安装在芯片焊盘（11）上的步骤中，当半导体元件（13）安装时，钎焊材料（19）从第一镀膜（14A）溢出 在熔融钎焊材料的上部。 然而，第二镀膜（14B）起到阻止钎焊材料溢出的阻挡区域的作用。 因此，由于已经扩展的钎焊材料，可以防止在芯片焊盘（11）和焊盘（12）之间产生短路。

公开(公告)号：US20040017419A1

公开(公告)日：2004-01-29

申请号：US10208163

申请日：2002-07-29

发明人： Diane Lai ,  Samson Berhane ,  Barry C. Snyder ,  Ronald A. Hellekson ,  Hubert Vander Plas

IPC分类号： B41J002/015 ,  H05K003/00 ,  C25D005/02 ,  C23C014/34 ,  H01L021/288 ,  H01L021/445 ,  B41N001/04 ,  B41C003/08 ,  H01B013/00 ,  G11B005/127 ,  G01D015/00 ,  H01L021/4763

CPC分类号： B41J2/16 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1634 ,  B41J2/1642 ,  B41J2/1643 ,  B41J2/1646 ,  B41J2202/18 ,  B81B7/0006 ,  B81B2201/052 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H05K1/112 ,  H05K2201/09518 ,  H01L2924/00

摘要： A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.

摘要翻译： 提供了一种制造微电子器件的方法，其中微电子器件形成在具有前侧和背侧的衬底上。 该方法包括从沉积在基板的前侧上的多个层在基板的前侧形成电路元件，其中多个层包括中间电接触层，以及在形成电接触层之后形成互连结构。 所述互连结构包括形成在所述衬底的背面上的接触焊盘以及与所述接触焊盘电连通的贯穿衬底互连，其中所述贯通衬底互连件从所述衬底的背面延伸到所述电接触层。