公开(公告)号：WO2006007141A2

公开(公告)日：2006-01-19

申请号：PCT/US2005017702

申请日：2005-05-19

申请人： FREESCALE SEMICONDUCTOR INC ,  BURNETTE TERRY E ,  KOSCHMIEDER THOMAS H

发明人： BURNETTE TERRY E ,  KOSCHMIEDER THOMAS H

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/60 ,  H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/544 ,  H01L29/40 ,  H05K1/02 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L22/34 ,  H01L24/81 ,  H01L2224/1181 ,  H01L2224/16 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/0269 ,  H05K3/3463 ,  H05K3/3489 ,  H05K2203/161 ,  H05K2203/163 ,  H01L2924/00

摘要： A solder system (14) includes a lead (Pb) indicator and a solder flux. A method for forming a semiconductor device includes providing a carrier (52), applying the solder system to the carrier (54), coupling the terminal to the carrier via the solder system (56), melting the solder system to attach the terminal to the carrier and form a completed semiconductor device (58), and determining if the completed semiconductor device has a different predetermined property from the solder system (60).

摘要翻译： 焊料系统（14）包括铅（Pb）指示剂和焊剂。 一种用于形成半导体器件的方法包括提供载体（52），将焊料系统施加到载体（54），通过焊料系统（56）将端子耦合到载体，熔化焊料系统以将端子附接到 并且形成完成的半导体器件（58），并且确定完成的半导体器件是否具有与焊料系统（60）不同的预定特性。

公开(公告)号：WO2006001564A1

公开(公告)日：2006-01-05

申请号：PCT/KR2004/003340

申请日：2004-12-17

申请人： HANMI SEMICONDUCTOR CO., LTD

发明人： JO, Yong-Chae

IPC分类号： H01L21/50

CPC分类号： H01L21/6838 ,  H05K13/0408

摘要： Disclosed is a semiconductor package picker. The semiconductor package picker does not seal a gap formed between a ball grid array (BGA) and a pad, but create strong negative pressure in the gap, thereby allowing the pad to pick up the semiconductor pad. The semiconductor package picker reliably picks up the BGA package even if the BGA is formed on an upper surface of the BGA package in addition to a bottom surface thereof.

摘要翻译： 公开了一种半导体封装拾取器。 半导体封装拾取器不会密封形成在球栅阵列（BGA）和焊盘之间的间隙，而是在间隙中产生强负压，从而允许焊盘拾取半导体焊盘。 即使BGA形成在BGA封装的上表面以外，半导体封装拾取器可靠地拾取BGA封装。

公开(公告)号：WO2004055885A8

公开(公告)日：2005-12-22

申请号：PCT/US0339766

申请日：2003-12-12

申请人： IC MECHANICS INC

发明人： CARLEY L RICHARD ,  HSU YU-NU ,  SANTHANAM SURESH

IPC分类号： B81B3/00 ,  B81B7/00 ,  G01P1/02 ,  G01P15/08 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： B81B7/0077 ,  B81B2203/0315 ,  B81C1/00476 ,  B81C1/00936 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01P1/023 ,  G01P15/0802 ,  G01P2015/0828

摘要： This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer (20). The process involves extending the layers of sacrificial material (12, 16) past the horizontal boundaries of the cap layer (20). The cap layer (20) is supported by pillars (21) formed by a deposition in holes etched through the sacrificial layers (12,16), and the etchant entry holes are formed when the excess sacrificial material (12, 16) is etched away, leaving voids between the pillars (21) supporting the cap.

摘要翻译： 本发明包括一种用于在密封空腔中制造MEMS微结构的方法，其中蚀刻剂入口孔作为制造工艺的副产品而产生，而没有额外的步骤来蚀刻盖层（20）中的孔。 该方法包括将牺牲材料层（12,16）延伸超过盖层（20）的水平边界。 盖层（20）由通过蚀刻通过牺牲层（12,16）蚀刻的孔中的沉积形成的柱支撑（21），并且当多余的牺牲材料（12,16）被蚀刻掉时形成蚀刻剂入口孔 在支撑盖子的支柱（21）之间留下空隙。

公开(公告)号：WO2005055310A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004012917

申请日：2004-11-15

申请人： SCHOTT AG ,  LEIB JUERGEN

发明人： LEIB JUERGEN

IPC分类号： H01L21/50 ,  H01L21/58 ,  H01L23/48

CPC分类号： H01L24/05 ,  H01L21/50 ,  H01L23/481 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/00015

摘要： The invention relates to a wafer level packaging process and to a component packaged in this way. It is an object of the invention to provide a process of this type which ensures a high yield, is also suitable for optical and/or micro­mechanical components and achieves improved thermo-mechanical decoupling of the connections from the functional regions. According to the process of the invention, the base substrate is divided into body regions and connection regions, the body regions in each case extending over the functional regions and the connection regions being offset with respect to the contact-connection recesses. The component is then thinned in the body regions or the connection regions until it has different thicknesses in the body regions and the connection regions, before the wafer assembly is diced into chips.

摘要翻译： 本发明涉及一种晶片级封装工艺以及以这种方式封装的部件。 本发明的目的是提供一种确保高产率的这种方法，也适用于光学和/或微机械部件，并且实现连接与功能区域的改进的热 - 机械去耦合。 根据本发明的方法，基底基板被分为主体区域和连接区域，每个壳体的主体区域在功能区域上延伸，并且连接区域相对于接触连接凹部偏移。 然后，在将晶片组装切成芯片之前，将部件在主体区域或连接区域中变薄，直到其在体区域和连接区域中具有不同的厚度。

公开(公告)号：WO2005070178A2

公开(公告)日：2005-08-04

申请号：PCT/US2005/000941

申请日：2005-01-12

申请人： FREESCALE SEMICONDUCTOR, INC. ,  COCHRAN, Patrick, B. ,  BAI, Zhi-Gang ,  CAO, Lu-Xin ,  CHOW, Wai Wong ,  KOVAR, Gary, J.

发明人： COCHRAN, Patrick, B. ,  BAI, Zhi-Gang ,  CAO, Lu-Xin ,  CHOW, Wai Wong ,  KOVAR, Gary, J.

IPC分类号： G01R31/28 ,  H01L21/50 ,  H01L21/66 ,  H01L23/544

CPC分类号： G01R31/2894 ,  H01L21/67242 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/0002 ,  H01L2924/00

摘要： A number of electronic die are attached to an interconnect structure (e.g., a lead frame, a substrate, a panel, or a strip). The die are encapsulated to provide a number of unsingulated packages of an overall package assembly. The unsingulated packages are then tested, and test results for each package are automatically marked on encapsulant corresponding to the package. The packages are then singulated after the automated machine marking, and sorted according to the markings.

摘要翻译： 多个电子管芯连接到互连结构（例如，引线框架，基板，面板或条）。 模具被封装以提供整个包装组件的许多未卷曲的包装。 然后测试未安装的软件包，并将每个软件包的测试结果自动标记在与软件包相对应的封装上。 然后将包装在自动机器标记之后进行分割，并根据标记进行分类。

公开(公告)号：WO2004097896A3

公开(公告)日：2005-05-06

申请号：PCT/US2004011873

申请日：2004-04-16

申请人： FREESCALE SEMICONDUCTOR INC ,  CHOPIN SHELIA F ,  HARPER PETER R ,  MONTES DE OCA JOSE A ,  TAN KIM HENG ,  TAN LAN CHU

发明人： CHOPIN SHELIA F ,  HARPER PETER R ,  MONTES DE OCA JOSE A ,  TAN KIM HENG ,  TAN LAN CHU

IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/495 ,  H01L21/30 ,  H01L21/301 ,  H01L21/44 ,  H01L21/46 ,  H01L21/48 ,  H01L21/50 ,  H01L23/28 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/4878 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48237 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： An integrated circuit (60) is packaged, in one embodiment, by wire bonding to pads (76, 78) supported by tape (83). The tape (83) also supports traces (80, 82) that run from the wire bonded location (76) to a pad for solder balls (90, 94). A heat spreader (69) is thermally connected to the integrated circuit (60) and is located not just in the area under the die (60) but also extends to the edge of the package in the area outside the wire bonding location. This outer area (68) is thermally connected to the area (66) under the die (60) by thermal bars (66) that run between some of the wire bond locations (76, 78). During the manufacturing of the package the heat spreader (69) is connected to slotted rails by tie bars (48, 50, 52, 54). During singulation, the tie bars (48, 50, 52, 54) are easily broken or sawed because they are significantly reduced in thickness from the thickness of the heat spreader (66) as a whole.

摘要翻译： 在一个实施例中，集成电路（60）通过引线接合到由磁带（83）支撑的焊盘（76,78）来封装。 带（83）还支撑从引线接合位置（76）延伸到用于焊球（90,94）的焊盘的迹线（80,82）。 散热器（69）热连接到集成电路（60），并且不仅位于管芯（60）下方的区域中，而且还在引线接合位置外部的区域中延伸到封装的边缘。 该外部区域（68）通过在一些引线接合位置（76,78）之间延伸的热棒（66）热连接到模具（60）下面的区域（66）。 在制造包装期间，散热器（69）通过连杆（48,50,52,54）连接到开槽轨道。 在分割期间，连杆（48,50,52,54）容易断裂或锯切，因为它们整体上与散热器（66）的厚度相比显着减小。

公开(公告)号：WO03100859A9

公开(公告)日：2005-04-07

申请号：PCT/EP0305415

申请日：2003-05-23

申请人： SCHOTT AG ,  LEIB JUERGEN ,  MUND DIETRICH

发明人： LEIB JUERGEN ,  MUND DIETRICH

IPC分类号： H05K3/46 ,  B81C1/00 ,  C03B19/00 ,  C03C4/12 ,  C03C14/00 ,  C03C15/00 ,  C03C17/02 ,  C03C17/34 ,  C23C14/10 ,  H01L21/316 ,  H01L21/50 ,  H01L21/56 ,  H01L21/768 ,  H01L23/10 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/532 ,  H01L23/66 ,  H01L51/52 ,  H01P11/00 ,  H05K3/28

CPC分类号： C03B19/00 ,  C03C3/083 ,  C03C3/089 ,  C03C4/12 ,  C03C14/006 ,  C03C15/00 ,  C03C17/02 ,  C03C17/34 ,  C03C2214/16 ,  C03C2217/21 ,  C03C2217/77 ,  C03C2218/15 ,  C03C2218/32 ,  C03C2218/328 ,  C03C2218/33 ,  C03C2218/355 ,  C23C14/10 ,  H01L21/02129 ,  H01L21/02145 ,  H01L21/02161 ,  H01L21/02263 ,  H01L21/31616 ,  H01L21/31625 ,  H01L21/50 ,  H01L21/56 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76885 ,  H01L23/10 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/97 ,  H01L51/5203 ,  H01L51/5237 ,  H01L51/5262 ,  H01L2223/6627 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/0106 ,  H01L2924/01061 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/19033 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/351 ,  H01P3/003 ,  H01P11/003 ,  H05K3/28 ,  H05K3/467 ,  H05K2201/0179 ,  Y02P40/57 ,  H01L2924/00

摘要： The invention relates to a method for producing a substrate (1) comprising a conductor assembly (4, 41, 42) that is suitable for use at high frequencies, said substrate having improved high-frequency characteristics. The method comprises the following steps: deposition of a structured glass layer (9, 91, 92, 93, 13) comprising at least one opening (8) above a contact region (71 - 74) by vapour deposition on the substrate (1); and application of at least one conductor structure (100, 111, 112, 113) to the glass layer (9, 91 - 93), which is in electric contact with the contact region (71 - 74).

摘要翻译： 本发明提供了一种具有高频合适的导体装置（4,41,42）的衬底（1）的制造方法，该装置具有改进的高频特性。 该方法包括以下步骤：通过在基板（1）上的气相沉积在接触区域（71-74）上沉积具有至少一个开口（8）的结构化玻璃层（9,91,92,93,13），并且施加至少一个 玻璃层（9,91-93）上的导体结构（100,111,112,113），其与接触区域（71-74）具有电接触。

公开(公告)号：WO2005024932A2

公开(公告)日：2005-03-17

申请号：PCT/JP2004/013281

申请日：2004-09-07

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. ,  KABESHITA, Akira ,  HAMASAKI, Kurayasu ,  MINAMITANI, Shozo ,  MAKINO, Yoichi ,  TANI, Noriyuki

发明人： KABESHITA, Akira ,  HAMASAKI, Kurayasu ,  MINAMITANI, Shozo ,  MAKINO, Yoichi ,  TANI, Noriyuki

IPC分类号： H01L21/50

CPC分类号： H01L21/67132 ,  Y10T156/1132 ,  Y10T156/1944

摘要： While a vicinity of a bottom surface-side region of a pressure-sensitive adhesive sheet (3) corresponding to an adhesion region (R1) of a semiconductor chip (1) are sucked and held, a plurality of protruding portions (30) of a removing member (21) are brought into contact with the bottom surface of the semiconductor chip through the adhesive sheet at the region. Also, the adhesive sheet is sucked in between the respective protruding portions so as to change a surface bonding of the semiconductor chip to the adhesive sheet by adhesion to a point bonding, and further the removing member is moved along the bottom surface of the semiconductor chip so as to change a position of the point bonding and decrease bonding force to the adhesive sheet by the adhesion. Then, the semiconductor chip is removed from the adhesive sheet.

摘要翻译： 在与半导体芯片（1）的粘合区域（R1）对应的粘合片（3）的底面侧区域附近被吸住并保持的情况下，将多个突起部（30） 移除部件（21）通过该区域的粘合片与半导体芯片的底面接触。 此外，粘合片被吸入各个突出部分之间，以便通过粘附到点粘合来改变半导体芯片与粘合片的表面粘合，并且还可以沿着半导体芯片的底面移动去除构件 从而通过粘合改变点粘合的位置并降低粘合力。 然后，将半导体芯片从粘合片上取出。

公开(公告)号：WO2004055885A3

公开(公告)日：2004-09-16

申请号：PCT/US0339766

申请日：2003-12-12

申请人： IC MECHANICS INC

发明人： CARLEY L RICHARD ,  HSU YU-NU ,  SANTHANAM SURESH

IPC分类号： B81B3/00 ,  B81B7/00 ,  G01P1/02 ,  G01P15/08 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： B81B7/0077 ,  B81B2203/0315 ,  B81C1/00476 ,  B81C1/00936 ,  B81C2201/0109 ,  B81C2201/0132 ,  B81C2203/0136 ,  G01P1/023 ,  G01P15/0802 ,  G01P2015/0828

摘要： This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer (20). The process involves extending the layers of sacrificial material (12, 16) past the horizontal boundaries of the cap layer (20). The cap layer (20) is supported by pillars (21) formed by a deposition in holes etched through the sacrificial layers (12,16), and the etchant entry holes are formed when the excess sacrificial material (12, 16) is etched away, leaving voids between the pillars (21) supporting the cap.

摘要翻译： 本发明包括一种用于在密封空腔中制造MEMS微结构的方法，其中蚀刻剂入口孔作为制造工艺的副产品而产生，而没有额外的步骤来蚀刻盖层（20）中的孔。 该方法包括将牺牲材料层（12,16）延伸超过盖层（20）的水平边界。 盖层（20）由通过蚀刻通过牺牲层（12,16）蚀刻的孔中的沉积形成的柱支撑（21），并且当多余的牺牲材料（12,16）被蚀刻掉时形成蚀刻剂入口孔 在支撑盖子的支柱（21）之间留下空隙。

公开(公告)号：WO2004064144A2

公开(公告)日：2004-07-29

申请号：PCT/GB2004000123

申请日：2004-01-15

申请人： ADVANCED INTERCONNECT TECH LTD ,  LUCAS BRIAN RONALD

发明人： ISLAM SHAFIDUL ,  SAN ANTONIO ROMARICO SANTOS

IPC分类号： H01L23/12 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L21/68 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50

CPC分类号： H01L21/4842 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is disclosed, wherein the method lends itself to better automation of the manufacturing line as well as to improving the quality and reliability of the packages produced therefrom. This is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, in contrast with the conventional fully etched stencil-like lead frames, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal. The use of the instant partially patterned lead frame in making ELP, ELPF and ELGA-type CSPs is also disclosed.

摘要翻译： 公开了一种制造引线框架和具有近芯片尺寸封装（CSP）引线计数的部分图案化引线框封装的方法，其中该方法有助于更好的自动化生产线以及提高质量和可靠性 的包装。 这是通过在与传统的完全蚀刻的模板状引线框架相反的情况下，通过在一侧上形成为网状引线框架的部分图案化的金属条进行制造工艺步骤的大部分来实现的， 类似的引线框架在另一侧上是坚固的和平坦的，在芯片级和封装级别的芯片附着和引线键合工艺期间也是刚性机械地和坚固的热的，以便不会发生变形或变形。 金属引线框架的底侧被图案化以隔离芯片焊盘，并且只有在包括芯片和电线在内的前侧之后，用密封剂气密地密封引线接合触点。 所得的封装被电隔离使得能够进行条带测试和可靠的分割，而不必切入任何额外的金属。 还公开了在制备ELP，ELPF和ELGA型CSP中使用即时部分图案化的引线框架。