摘要:
Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
摘要:
A semiconductor device (200) configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising: a lead frame (210) including a first set of leads (220,222,224,226) and a second set of leads (230,232,234,236), the first set of leads being isolated from the second set of leads; a semiconductor die (240) positioned on the lead frame (210); an isolating block (250) positioned on the semiconductor die; a first interconnect coil (202) formed by a first set of wires (260,262,264,266), the semiconductor die, and the first set of leads; and a second interconnect coil (204) isolated from the first interconnect coil and formed by a second set of wires (280,282,284,286), the isolating block, and the second set of leads.
摘要:
An integrated circuit (IC) device arrangement includes a substrate (202), an IC die (204) coupled to the substrate, an antenna (206) coupled to the IC die, and a first wirelessly enabled functional block (210) coupled to the IC die. The wirelessly enabled functional block is configured to wirelessly communicate with a second wirelessly enabled functional block (212) coupled to the substrate. The antenna is configured to communicate with another antenna coupled to another device.
摘要:
With respect to a semiconductor device which communicates data by wireless communication, an object of the present invention is to improve sensitivity of an antenna and to protect a chip from noise without increasing the size of the device. A coiled antenna and a semiconductor integrated circuit which is electrically connected to the coiled antenna are included. The semiconductor integrated circuit is arranged so as to overlap with the coiled antenna. In this manner, arrangement of the coiled antenna and the semiconductor integrated circuit in the semiconductor device is devised, so that sensitivity of the antenna can be improved and power enough to operate the semiconductor integrated circuit can be obtained without increasing the size of the device.
摘要:
A bond wire circuit includes bond wires arranged relatively to provide a selected inductance. In connection with various example embodiments, respective bond wire loops including forward and return current paths are arranged orthogonally. Each loop includes a forward bond wire connecting an input terminal with an intermediate terminal, and a return bond wire connecting the intermediate terminal to an output terminal. The return bond wires generally mitigate return current flow from the intermediate terminal in an underlying substrate. In some implementations, the loops are arranged such that current flowing in each of the respective loops generates equal and self-cancelling current in the other of the respective loops.
摘要:
A semiconductor device configured to provide current and voltage isolation inside an integrated circuit package, the semiconductor device comprising: a lead frame including a first set of leads and a second set of leads, the first set of leads being isolated from the second set of leads; a semiconductor die positioned on the lead frame; an isolating block positioned on the semiconductor die; a first interconnect coil formed by a first set of wires, the semiconductor die, and the first set of leads; and a second interconnect coil isolated from the first interconnect coil and formed by a second set of wires, the isolating block, and the second set of leads.
摘要:
. An integrated circuit chip comprising: - a silicon substrate; - a first dielectric layer over said silicon substrate; - a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer,wherein said metallization structure comprises electroplated copper; - a second dielectric layer between said first and second metal layers; - a separating layer over said metallization structure and over said first and second dielectric layers, wherein said separating layer comprises a nitride layer having a thickness between 0.5 and 2 micrometers; - a third metal layer over said separating layer, wherein said third metal layer comprises at least a portion, vertically over said separating layer, of an inductor, wherein said third metal layer comprises electroplated copper; and - a first polymer layer over said third metal layer.
摘要:
A module that can not only achieve the reduction in size and manufacturing cost but also be impervious to noise due to electromagnetic waves, and a mounted structure using the same are provided. A module (1) includes a substrate (12) and a plurality of semiconductor packages (11a, 11b), each including a semiconductor chip (10), mounted on the substrate (12). Each of the plurality of semiconductor packages (11a, 11b) includes a first radio communication element (16) for transmitting and receiving a signal between the semiconductor chips (10) in the plurality of semiconductor packages (11a, 11b) by radio communication, and the first radio communication element (16) is constituted independently of the semiconductor chip (10).
摘要:
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
摘要:
Various on-chip capacitors and methods of making the same are disclosed. In one aspect, a method of manufacturing a capacitor is provided that includes forming a first conductor structure on a semiconductor chip and forming a passivation structure on the first conductor structure. An under bump metallization structure is formed on the passivation structure. The under bump metallization structure overlaps at least a portion of the first conductor structure to provide a capacitor.