公开(公告)号：JP4276784B2

公开(公告)日：2009-06-10

申请号：JP2000550311

申请日：1999-05-03

Applicant: エプコス アクチエンゲゼルシャフトEpcos Ag

Inventor： シュテルツル アロイス ,  ヴァイトナー カール ,  クリューガー ハンス ,  ヴォスラー マンフレート

IPC: H05K3/00 ,  H01L21/48 ,  H01L23/498 ,  H03H3/00 ,  H05K1/02 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/403 ,  H01L21/4853 ,  H01L23/49805 ,  H01L23/49816 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H03H3/00 ,  H05K1/0243 ,  H05K3/0052 ,  H05K3/242 ,  H05K3/245 ,  H05K3/3442 ,  H05K3/3473 ,  H05K3/42 ,  H05K2201/09181 ,  H05K2201/09481 ,  H05K2201/10083 ,  H05K2203/043 ,  H05K2203/1572 ,  H01L2224/81

公开(公告)号：JP2009081342A

公开(公告)日：2009-04-16

申请号：JP2007250675

申请日：2007-09-27

Applicant: Sharp Corp ,  シャープ株式会社

Inventor： UENO YUKIHIRO

IPC: H05K3/46

CPC classification number: H05K3/4691 ,  H05K1/117 ,  H05K1/148 ,  H05K3/4652 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/2009 ,  Y10T29/49147

Abstract: PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board having a high quality terminal part formed. SOLUTION: The multilayer printed wiring board 1 includes a flexible part 2 which is soft and can be bent for use, a rigid part 3 formed in connection with the flexible part 2 and more rigid than the flexible part 2, and the terminal part 4 formed at an end of the flexible part 2 in connection with the part 2. The rigid part 3 contains an insulative rigid layer 6. The terminal part 4 contains an insulative layer 8 made of the same material as that of the rigid layer 6, and also has a conductor layer 9 formed in a terminal pattern to serve as a connection terminal on the surface of the insulative layer 8. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种形成有高质量端子部分的多层印刷线路板。 解决方案：多层印刷线路板1包括柔性并可弯曲使用的柔性部分2，与柔性部分2相连并且比柔性部分2更刚性地形成的刚性部分3和终端 部分4形成在柔性部分2的与部分2相关的端部处。刚性部分3包含绝缘刚性层6.端子部分4包含由与刚性层6相同的材料制成的绝缘层8 并且还具有形成在端子图案中的导体层9，以用作绝缘层8的表面上的连接端子。（C）2009，JPO＆INPIT

公开(公告)号：JP2009004744A

公开(公告)日：2009-01-08

申请号：JP2008110433

申请日：2008-04-21

Applicant: Samsung Electro Mech Co Ltd ,  三星電機株式会社

Inventor： KANG MYUNG SAM ,  KIM CHIN KWAN

IPC: H05K3/34 ,  H01L21/60 ,  H05K1/11 ,  H05K3/38 ,  H05K3/40

CPC classification number: H05K3/4007 ,  H05K3/246 ,  H05K3/3457 ,  H05K3/4069 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09745

Abstract: PROBLEM TO BE SOLVED: To provide a printed-circuit board which improves the adhesion between IC and the board by increasing the area of contact between them.
SOLUTION: The printed-circuit board comprises an insulating layer 2 wherein a first circuit pattern 4 including at least one or more via lands 4a is embedded in the upper part so that it has the same surface as the upper surface, while a second circuit pattern 8 formed at a position corresponding to the via land 4a is embedded in the lower part so that it has the same surface as the lower surface, a solder resist layer 12 which is laminated on the insulating layer 2, a via hole 6 which is formed in the insulating layer 2 so as to connect electrically the via land 4a and the second circuit pattern 8, and a bump 10 which is formed in an integrated type on the second circuit pattern 8 so that it pierces the via hole 6 and the via land 4a, and is provided in projection on the upper surface of the insulating layer 2 so that it has a height above the solder resist layer 12.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种印刷电路板，其通过增加它们之间的接触面积来提高IC和板之间的粘附性。 解决方案：印刷电路板包括绝缘层2，其中包括至少一个或多个通孔焊盘4a的第一电路图案4嵌入在上部中，使得其具有与上表面相同的表面，而 形成在与通孔接合区域4a相对应的位置的第二电路图案8嵌入下部，使其具有与下表面相同的表面，层叠在绝缘层2上的阻焊层12，通孔6 其形成在绝缘层2中，以便电连接通路接合区域4a和第二电路图案8，以及在第二电路图案8上形成为集成型的突起10，以使其穿透通孔6和 通孔焊盘4a，并且设置在绝缘层2的上表面上的突起中，使得其具有高于阻焊层12的高度。版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008227387A

公开(公告)日：2008-09-25

申请号：JP2007066900

申请日：2007-03-15

Applicant: Elpida Memory Inc ,  Hitachi Ltd ,  エルピーダメモリ株式会社 ,  株式会社日立製作所

Inventor： UEMATSU YUTAKA ,  SAITO TATSUYA ,  OSAKA HIDEKI ,  NISHIO YOJI ,  SAITO SHUNICHI

IPC: H01L23/12

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which actualize a power supply path having a low antiresonance impedance in several 10 MHz band, reduces a power supply noise, can obtain a low impedance in a low frequency band and an impedance profile with a low antiresonance impedance even in a middle frequency band, to actualize a low power supply noise and speed-up in the power supply path in a semiconductor chip. SOLUTION: The antiresonance impedance in the middle frequency band is reduced effectively while the low impedance is maintained by introducing a structure for making a resistance value high in the middle frequency band into parts such as power supply wirings and a capacitor mounting electrode in the semiconductor package 1, which have a relatively high resistance value by nature. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供实现在几个10MHz频带中具有低反共振阻抗的电源路径的半导体器件，降低了电源噪声，可以获得低频带中的低阻抗和阻抗曲线 即使在中频带中也具有低反谐振阻抗，以实现半导体芯片中的电源路径中的低电源噪声和加速。 解决方案：通过在中频带引入电阻值高的结构，将电源配线和电容器安装电极等部分引入，能够有效地降低中频带的反谐振阻抗，同时保持低阻抗 半导体封装1本质上具有相对较高的电阻值。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008218441A

公开(公告)日：2008-09-18

申请号：JP2007049193

申请日：2007-02-28

Applicant: Micronics Japan Co Ltd ,  株式会社日本マイクロニクス

Inventor： FUKAMI YOSHIYUKI

IPC: H05K3/46 ,  G01R31/02

CPC classification number: H05K1/0268 ,  G01R31/2805 ,  G01R31/2812 ,  H05K1/0306 ,  H05K3/4605 ,  H05K2201/09481 ,  H05K2201/09845

Abstract: PROBLEM TO BE SOLVED: To measure the capacitance of wiring without providing a whole surface ground layer in a multilayer wiring portion inherent to each kind by providing an internal conductor layer in a base substrate. SOLUTION: A multilayer wiring portion 11 is formed on a ceramic substrate 10. The ceramic substrate 10 has an internal conductor layer 14 connected with an inspection pad 16. At a stage when a first conductor layer 12 is formed, capacitance is measured between the wiring pattern 22 of the first conductor layer and the inspection pad 16. On the other hand, the capacitance is calculated in case of a normal wiring pattern 22. A judgment is made whether the wiring pattern 22 is abnormal or not by comparing the measurement with a calculated value. Measurement and comparison are performed similarly for second through fifth conductor layers and then a judgment is made whether the wiring pattern 22 is abnormal or not for the three-dimensional wiring route. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：通过在基底基板中设置内部导体层，来测量在各种固有的多层布线部分中没有提供整个表面接地层的布线的电容。 解决方案：在陶瓷基板10上形成多层布线部分11.陶瓷基板10具有与检查焊盘16连接的内部导体层14.在形成第一导体层12的阶段，测量电容 在第一导体层的布线图形22和检查焊盘16之间。另一方面，在正常布线图案22的情况下计算电容。通过比较布线图案22是否异常来判断布线图案22是否异常 用计算值进行测量。 对第二至第五导体层进行同样的测量和比较，然后判断布线图案22是否为三维布线路线异常。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008042154A

公开(公告)日：2008-02-21

申请号：JP2006264172

申请日：2006-09-28

Applicant: Kinko Denshi Kofun Yugenkoshi ,  欣興電子股▲ふん▼有限公司

Inventor： TEI SHINKA

IPC: H01L23/12

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/056 ,  H05K3/4608 ,  H05K3/4641 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: PROBLEM TO BE SOLVED: To provide a package board which satisfies requirements from the standpoint of manufacturing process by combining a reinforcing plate to enhance strength of a thin board.
SOLUTION: The package board 200 is provided in which a circuit board 210, a reinforcing plate 240, and at least one conductive groove 250 are arranged. The reinforcing plate is so arranged that a first surface 240a contacts the circuit board, preventing warping of the circuit board. The reinforcing plate comprises an opening which corresponds to the first contact of the circuit board and is exposed in the opening. One end of the conductive groove is positioned in the opening and is electrically connected to the first connected, and the other end of the conductive groove is positioned at a second surface 240b of the reinforcing plate, forming a bonding pad.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种从制造过程的观点出发，通过组合加强板来提高薄板的强度来满足要求的封装板。 解决方案：提供了包括电路板210，加强板240和至少一个导电槽250的封装板200。 加强板的布置使得第一表面240a接触电路板，防止电路板翘曲。 加强板包括对应于电路板的第一接触并暴露在开口中的开口。 导电槽的一端位于开口中并与第一连接电连接，导电槽的另一端位于加强板的第二表面240b处，形成接合焊盘。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007180384A

公开(公告)日：2007-07-12

申请号：JP2005378948

申请日：2005-12-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： YAMAJI YOSHIYUKI ,  NOMAN YUICHI ,  MORI HIROYUKI

IPC: H01L23/12 ,  H01L21/60

CPC classification number: H01L21/6835 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/11003 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/30105 ,  H05K1/0216 ,  H05K3/4015 ,  H05K3/4602 ,  H05K2201/0367 ,  H05K2201/0792 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09909 ,  H05K2201/09981 ,  H05K2203/0113 ,  H05K2203/0235 ,  H05K2203/0338 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor package which has superior high-frequency characteristics and can increase the area of an internal wiring pattern. SOLUTION: The semiconductor package is equipped with a multilayer printed wiring board 12, an IC chip mounted on its surface, and a plurality of bump terminals 16 mounted on the reverse surface of the multilayer printed wiring board 12. Each of the bump terminals 16 includes an insulating core 42 having a plane 40, and a conductive film 44 formed on a surface other than the plane 40. The end surface of the conductive film 44 appears annularly at the circumference of the insulating core 42, and is soldered to an annular connection pad 52 formed on the reverse surface of the multilayer printed wiring board 12. A via hole 36 is formed right above the bump terminal 16, and a clearance hole 34 that the via hole 36 runs through is formed in internal wiring patterns 28 and 30. The diameter of the clearance hole 34 is made smaller than the diameter of the bump terminal 16. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有优异的高频特性并且可以增加内部布线图案的面积的半导体封装。 解决方案：半导体封装配备有多层印刷线路板12，安装在其表面上的IC芯片和安装在多层印刷线路板12的背面上的多个凸点端子16.每个凸起 端子16包括具有平面40的绝缘芯42和形成在除了平面40之外的表面上的导电膜44.导电膜44的端表面环形地出现在绝缘芯42的圆周处，并被焊接到 形成在多层印刷布线板12的背面上的环形连接焊盘52.在凸块端子16正上方形成有通孔36，通孔36穿过的间隙孔34形成在内部布线图形28中 间隙孔34的直径小于凸块端子16的直径。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：JP2007173727A

公开(公告)日：2007-07-05

申请号：JP2005372614

申请日：2005-12-26

Applicant: Shinko Electric Ind Co Ltd ,  新光電気工業株式会社

Inventor： KYOZUKA MASAHIRO

IPC: H05K3/46

CPC classification number: H05K3/0097 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K3/007 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/4007 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0113 ,  H05K2203/0152 ,  H05K2203/0338 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T156/1062 ,  H01L2224/05599

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board whereon wiring patterns with excellent dimensional precision can be formed without causing a step difference to an insulation layer. SOLUTION: In the method of manufacturing the wiring board wherein two metallic base members 10, one-side faces of which are opposed to each other are adhered to each other, a multi-layered wiring board is formed to the other sides of the respective base members 10, then both the base members 10 are separated from each other and thereafter, the respective base members 10 are removed from the multi-layered wiring boards to manufacture the independent wireless boards, when the two base members 10 are adhered, a liquid mold release is coated or printed onto parts of the two base members 10 except circumference ridges of each one side, an adhesive resin sheet 11 is inserted between the two base members 10, and the circumference ridges of the base members 10 to which no mold release is adhered are adhered to and joined with each other. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造布线板的方法，其中可以形成具有优异尺寸精度的布线图案而不会对绝缘层造成阶梯差。 解决方案：在制造其一侧面彼此相对的两个金属基底构件10的布线板的制造方法中，将多层布线板形成在另一侧 相应的基部构件10，然后两个基底构件10彼此分离，然后，当粘合两个基底构件10时，各个基底构件10从多层布线板去除以制造独立的无线基板， 将液体脱模剂涂布或印刷到除了每一侧的圆周脊之外的两个基底构件10的部分上，粘合树脂片11插入在两个基底构件10之间，并且基底构件10的圆周脊没有 粘合的脱模剂彼此粘附并接合。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007173386A

公开(公告)日：2007-07-05

申请号：JP2005366789

申请日：2005-12-20

Applicant: Fujitsu Ltd ,  富士通株式会社

Inventor： KURIHARA KAZUAKI ,  SHIOGA KENJI ,  BANIECKI JOHN DAVID ,  ISHII MASATOSHI

IPC: H01L21/822 ,  H01G4/12 ,  H01L23/12 ,  H01L27/04 ,  H05K1/16

CPC classification number: H01L23/5223 ,  H01G4/33 ,  H01L23/3114 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L28/55 ,  H01L28/65 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/185 ,  H05K2201/0179 ,  H05K2201/09481 ,  H05K2201/10712 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a thin film capacitor capable of surely preventing a capacitor dielectric film from being reduced by hydrogen and water content, as well as a manufacturing method thereof, an electronic equipment using the same, and a circuit board. SOLUTION: The thin film capacitor comprises a capacitor device 20 which is formed on a support substrate 10 and comprises a first capacitor electrode 14, a capacitor dielectric film 16 formed on the first capacitor electrode, and a second capacitor electrode 18 formed on the capacitor dielectric film. It also comprises drawn-out electrodes 26a and 26b consisting of a conductive barrier film that prevents diffusion of hydrogen or water content and is drawn out of the first capacitor electrode or second capacitor electrode, and external connection electrodes 34a and 34b connected to the drawn-out electrodes. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：为了提供一种能够可靠地防止电容器电介质膜被氢和水分含量减少的薄膜电容器及其制造方法，使用该薄膜电容器的电子设备和电路板 。 解决方案：薄膜电容器包括形成在支撑基板10上的电容器装置20，其包括第一电容器电极14，形成在第一电容器电极上的电容器电介质膜16和形成在第一电容器电极上的第二电容器电极18 电容电介质膜。 它还包括由阻止氢或水含量扩散并从第一电容器电极或第二电容器电极引出的导电阻挡膜构成的引出电极26a和26b，以及连接到拉制电极的外部连接电极34a和34b， 出电极。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP3934400B2

公开(公告)日：2007-06-20

申请号：JP2001341588

申请日：2001-11-07

Applicant: アルプス電気株式会社

Inventor： 秀晴 大竹 ,  典雄 鈴木

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/02 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K3/366 ,  H05K3/3468 ,  H05K2201/048 ,  H05K2201/09481 ,  H05K2201/0999 ,  H05K2203/0455 ,  H05K2203/167