Patent search ap:("Samsung Electronics Co. Page Ltd.") AND inv:"Hyun-soo Chung"

1.

发明授权
Semiconductor packages 有权

公开(公告)号：US10438899B2

公开(公告)日：2019-10-08

申请号：US15869517

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim , Hyun-soo Chung , Dong-hyeon Jang

IPC: H01L23/552 , H01L23/538 , H01L23/00 , H01L23/34 , H01L23/367 , H01L23/433 , H01L25/065 , H01L25/10

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

2.

发明申请
SEMICONDUCTOR PACKAGES 审中-公开

公开(公告)号：US20190237410A1

公开(公告)日：2019-08-01

申请号：US16381319

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong KIM , Hyun-soo Chung , Dong-hyeon Jang

IPC: H01L23/552 , H01L23/00 , H01L23/34 , H01L23/538 , H01L23/367 , H01L23/433

CPC classification number: H01L23/552 , H01L23/345 , H01L23/367 , H01L23/4334 , H01L23/5384 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2224/12105 , H01L2224/13025 , H01L2224/16146 , H01L2224/16227 , H01L2224/17181 , H01L2224/2919 , H01L2224/2929 , H01L2224/29339 , H01L2224/29344 , H01L2224/29347 , H01L2224/29355 , H01L2224/32145 , H01L2224/32245 , H01L2224/48227 , H01L2224/73204 , H01L2224/73267 , H01L2224/83851 , H01L2224/83862 , H01L2224/83874 , H01L2224/92244 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3025 , H01L2924/3511 , H01L2224/83 , H01L2924/0665 , H01L2924/069 , H01L2924/0635

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

3.

发明申请
STACKED SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开

公开(公告)号：US20170117264A1

公开(公告)日：2017-04-27

申请号：US15285500

申请日：2016-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-young Lee , Hyun-soo Chung , Tae-je Cho

IPC: H01L25/00 , H01L23/00

CPC classification number: H01L25/50 , H01L21/561 , H01L21/568 , H01L23/5384 , H01L23/5389 , H01L24/03 , H01L24/17 , H01L24/19 , H01L24/20 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/0231 , H01L2224/02379 , H01L2224/04105 , H01L2224/12105 , H01L2224/32145 , H01L2224/73267 , H01L2225/1035 , H01L2225/1058 , H01L2924/18162

Abstract: A method may include providing a first semiconductor chip and a first insulating layer surrounding lateral sides of the first semiconductor chip; providing a second semiconductor chip and a second insulating layer surrounding lateral sides of the second semiconductor chip; providing a third insulating layer below the first semiconductor chip and first insulating layer, so that the first semiconductor chip is between the third insulating layer and the second semiconductor chip, the third insulating layer forming a package substrate; providing a plurality of external connection terminals on the third insulating layer, such that the third insulating layer has a first surface facing the first semiconductor chip and a second surface facing the external connection terminals; providing a first redistribution line on the first surface of the third insulating layer and extending horizontally along the first surface of the third insulating layer, the first redistribution line contacting a first conductive pad of the first semiconductor chip; and providing a second redistribution line connected to a second conductive pad at a surface of the second semiconductor chip, the second redistribution line passing through the first insulating layer to contact the first redistribution line.

4.

发明授权
Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages 有权

公开(公告)号：US09698051B2

公开(公告)日：2017-07-04

申请号：US14590036

申请日：2015-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-ho Chun , Byung-Iyul Park , Hyun-soo Chung , Gil-heyun Choi , Son-kwan Hwang

IPC: H01L23/52 , H01L23/48 , H01L29/24 , H01L21/768 , H01L25/065 , H01L23/544 , H01L23/00 , H01L23/31

CPC classification number: H01L21/76898 , H01L21/768 , H01L21/76841 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/03 , H01L24/81 , H01L25/065 , H01L25/0657 , H01L2223/54426 , H01L2224/03462 , H01L2224/0401 , H01L2224/05 , H01L2224/05025 , H01L2224/05552 , H01L2224/0557 , H01L2224/06181 , H01L2224/13 , H01L2224/13023 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/8185 , H01L2924/00014 , H01L2924/06 , H01L2924/12042 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

5.

发明申请
SEMICONDUCTOR DEVICES INCLUDING DUMMY SOLDER BUMPS 审中-公开
Title translation: 半导体器件包括DUMMY SOLDER BUMPS

公开(公告)号：US20130221519A1

公开(公告)日：2013-08-29

申请号：US13753774

申请日：2013-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Son-kwan Hwang , Byung-Iyul Park , Hyun-soo Chung , Jin-ho Chun , Gil-heyun Choi

IPC: H01L23/498

CPC classification number: H01L23/49811 , H01L21/561 , H01L23/3107 , H01L24/11 , H01L24/14 , H01L2224/16225 , H01L2224/17517 , H01L2924/15311

Abstract: A semiconductor device includes a substrate on which integrated circuit units are formed, main solder bumps that are electrically connected to the integrated circuit units on the substrate and dummy solder bumps that are not electrically connected to the integrated circuit units on the substrate. The dummy solder bumps are narrower than wiring patterns immediately below the dummy solder bumps.

Abstract translation: 半导体器件包括其上形成有集成电路单元的基板，与基板上的集成电路单元电连接的主要焊料凸块和未电连接到基板上的集成电路单元的虚拟焊料凸块。虚拟焊料凸块比虚拟焊料凸块正下方的布线图形窄。

6.

发明授权
Semiconductor packages 有权

公开(公告)号：US11031347B2

公开(公告)日：2021-06-08

申请号：US16381319

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim , Hyun-soo Chung , Dong-hyeon Jang

IPC: H01L23/552 , H01L23/538 , H01L23/00 , H01L23/34 , H01L23/367 , H01L23/433 , H01L25/065 , H01L25/10 , H01L23/498

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

7.

发明授权
Method of manufacturing semiconductor package 有权
Title translation: 制造半导体封装的方法

公开(公告)号：US09412707B2

公开(公告)日：2016-08-09

申请号：US14702662

申请日：2015-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-soo Chung , Tae-je Cho , Jung-seok Ahn , In-young Lee

IPC: H01L29/40 , H01L23/00 , H01L23/48 , H01L21/78 , H01L21/304 , H01L21/683 , H01L25/00 , H01L25/065 , H01L21/768 , H01L21/48 , H01L23/31 , H01L21/56

CPC classification number: H01L23/562 , H01L21/304 , H01L21/4803 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/76898 , H01L21/78 , H01L23/3114 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68381 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/97 , H01L2924/15311 , H01L2924/181 , H01L2924/00012

Abstract: Embodiments of the inventive aspect include a method of manufacturing a semiconductor package including a plurality of stacked semiconductor chips in which edges of a semiconductor wafer substrate may be prevented from being damaged or cracked when the semiconductor package is manufactured at a wafer level, while a diameter of a molding element is greater than a diameter of the semiconductor wafer substrate. The molding element may cover a surface of the wafer substrate and the plurality of stacked semiconductor chips. Embodiments may include a wafer level semiconductor package including a circular substrate having a first diameter, a circular passivation layer attached to the circular substrate, the passivation layer having the first diameter, and a circular molding element covering surfaces of the plurality of semiconductor chips, and covering an active area of the substrate. The circular molding element may have a second diameter that is greater than the first diameter.

Abstract translation: 本发明的实施例包括一种制造半导体封装的方法，该半导体封装包括多个层叠半导体芯片，其中半导体封装在晶片级制造时可以防止半导体晶片衬底的边缘损坏或破裂，而直径的模制元件的直径大于半导体晶片衬底的直径。成型元件可以覆盖晶片基板的表面和多个堆叠的半导体芯片。实施例可以包括晶片级半导体封装，其包括具有第一直径的圆形衬底，附着到圆形衬底的圆形钝化层，具有第一直径的钝化层和覆盖多个半导体芯片的表面的圆形模制元件，以及覆盖基板的有效区域。圆形模制元件可以具有大于第一直径的第二直径。

8.

发明申请
Semiconductor Chips Having Through Silicon Vias and Related Fabrication Methods and Semiconductor Packages 有权
Title translation: 具有硅通孔和相关制造方法和半导体封装的半导体芯片

公开(公告)号：US20130264720A1

公开(公告)日：2013-10-10

申请号：US13733923

申请日：2013-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-ho Chun , Byung-lyul Park , Hyun-soo Chung , Gil-heyun Choi , Son-kwan Hwang

IPC: H01L23/48 , H01L21/768

CPC classification number: H01L21/76898 , H01L21/768 , H01L21/76841 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/03 , H01L24/81 , H01L25/065 , H01L25/0657 , H01L2223/54426 , H01L2224/03462 , H01L2224/0401 , H01L2224/05 , H01L2224/05025 , H01L2224/05552 , H01L2224/0557 , H01L2224/06181 , H01L2224/13 , H01L2224/13023 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/8185 , H01L2924/00014 , H01L2924/06 , H01L2924/12042 , H01L2924/15311 , H01L2924/15788 , H01L2924/181 , H01L2924/18161 , H01L2924/00

Abstract: A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.

Abstract translation: 包括通过硅通孔（TSV）的半导体芯片，其中可以防止TSV弯曲，并且可以简化制造半导体芯片的方法，以及制造半导体芯片的方法。半导体芯片包括具有第一表面和第二表面的硅衬底; 多个TSV，其穿透硅衬底并突出在硅衬底的第二表面上方; 形成在硅衬底的第二表面上的聚合物图案层围绕每个TSV的突出部分的侧表面，并且包括平坦的第一部分和在第一部分上方突出的第二部分; 以及形成在聚合物图案层上并覆盖从聚合物图案层露出的每个TSV的一部分的电镀垫。