公开(公告)号：US09595619B2

公开(公告)日：2017-03-14

申请号：US14821969

申请日：2015-08-10

Applicant: Infineon Technologies AG

Inventor： Holger Hüsken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Rösner ,  Holger Schulze

IPC: H01L29/872 ,  H01L29/417 ,  H01L29/66 ,  H01L29/47 ,  H01L29/32 ,  H01L29/45 ,  H01L29/868 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/872 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/868

Abstract: A semiconductor device includes at least one first contact region of a vertical device between a semiconductor substrate and an electrically conductive structure arranged adjacent to the semiconductor substrate, and at least one second contact region of the vertical device between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one first contact region is arranged adjacent to the at least one second contact region. The electrically conductive structure includes a first electrically conductive material in contact with the semiconductor substrate in an area of the at least one first contact region and a second electrically conductive material in contact with the semiconductor substrate in an area of the at least one second contact region, so that a first contact characteristic within the at least one first contact region differs from a second contact characteristic within the at least one second contact region.

Abstract translation: 半导体器件包括在半导体衬底和邻近半导体衬底布置的导电结构之间的垂直器件的至少一个第一接触区域，以及垂直器件的至少一个第二接触区域，位于半导体器件的半导体衬底和 导电结构。 所述至少一个第一接触区域布置成与所述至少一个第二接触区域相邻。 所述导电结构包括在所述至少一个第一接触区域的区域中与所述半导体衬底接触的第一导电材料和在所述至少一个第二接触区域的区域中与所述半导体衬底接触的第二导电材料 使得所述至少一个第一接触区域内的第一接触特性与所述至少一个第二接触区域内的第二接触特性不同。

公开(公告)号：US09543398B2

公开(公告)日：2017-01-10

申请号：US14814758

申请日：2015-07-31

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Anton Mauder ,  Matteo Dainese ,  Franz Hirler ,  Christian Jaeger ,  Maximilian Roesch ,  Wolfgang Roesner ,  Martin Stiftinger ,  Robert Strenz

IPC: H01L29/423 ,  H01L27/02 ,  H01L27/06 ,  H01L27/115 ,  H01L29/792 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42344 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/0623 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0619 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/42376 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/7883 ,  H01L29/792

Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.

Abstract translation: 半导体开关器件包括电连接到晶体管单元的源极区的第一负载端子。 源区与身体区形成第一个pn结。 第二负载端子电连接到与主体区域形成第二pn结的排水构造。 包括控制电极和电荷存储结构的控制结构直接与身体区相邻。 控制电极控制穿过身体区域的负载电流。 电荷存储结构将控制电极与体区绝缘，并且在控制电极和第一负载电极之间没有电位差的情况下，包含适于在体区中诱导反转通道的控制电荷。

公开(公告)号：US20160225856A1

公开(公告)日：2016-08-04

申请号：US15097114

申请日：2016-04-12

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hans-Joachim Schulze ,  Anton Mauder ,  Wolfgang Lehnert ,  Günther Ruhl ,  Roland Rupp

IPC: H01L29/16 ,  H01L23/29

CPC classification number: H01L29/1608 ,  H01L21/02002 ,  H01L21/02376 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02491 ,  H01L21/02529 ,  H01L21/2007 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/56 ,  H01L23/291 ,  H01L23/298 ,  H01L29/1075 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A composite wafer includes a substrate and a SiC-based functional layer. The substrate includes a porous carbon substrate core and an encapsulating layer encapsulating the substrate core. The SiC-based functional layer comprises, at an interface region with the encapsulating layer, at least one of: a carbide and a silicide formed by reaction of a portion of the SiC-based functional layer with a carbide-and-silicide-forming metal. An amount of the carbide-and-silicide-forming metal, integrated over the thickness of the functional layer, is 10−4 mg/cm2 to 0.1 mg/cm2.

Abstract translation: 复合晶片包括基板和SiC基功能层。 衬底包括多孔碳衬底芯和封装衬底芯的封装层。 所述SiC基功能层在与所述封装层的界面区域处包含以下中的至少一种：碳化物和由所述SiC基功能层的一部分与碳化物和硅化物形成金属反应形成的硅化物 。 在功能层的厚度上积分的碳化物和硅化物形成金属的量为10-4mg / cm 2至0.1mg / cm 2。

公开(公告)号：US20160086844A1

公开(公告)日：2016-03-24

申请号：US14962393

申请日：2015-12-08

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze ,  Karsten Kellermann ,  Michael Sommer ,  Christian Rottmair ,  Roland Rupp

IPC: H01L21/762 ,  H01L21/321 ,  H01L21/265 ,  H01L29/20 ,  H01L21/324 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L21/76254 ,  C30B25/186 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02598 ,  H01L21/2007 ,  H01L21/265 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76251 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003

Abstract: A composite wafer is manufactured by providing a carrier wafer including graphite and a protective layer, forming a bonding layer, and bonding the carrier wafer to a semiconductor wafer through the bonding layer.

Abstract translation: 通过提供包括石墨和保护层的载体晶片来形成复合晶片，形成结合层，并通过粘合层将载体晶片接合到半导体晶片。

公开(公告)号：US09165792B2

公开(公告)日：2015-10-20

申请号：US13625893

申请日：2012-09-25

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Anton Mauder

IPC: H01L23/48 ,  H01L21/50 ,  H01L23/31 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68377 ,  H01L2224/03462 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/08145 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27416 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/80203 ,  H01L2224/80801 ,  H01L2224/80893 ,  H01L2224/80894 ,  H01L2224/83805 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area.

Abstract translation: 提供集成电路，集成电路包括：载体，其包括至少一个电子部件和布置在载体的第一侧上的至少一个接触区域，其中至少一个电子部件电连接到该至少一个触点 区; 与所述载体的第一侧接合的无机材料层晶片，其中所述载体具有第一热膨胀系数，并且其中所述无机材料层具有第二热膨胀系数，其中所述第二热膨胀系数具有 与第一热膨胀系数相比低于100％; 以及通过无机材料层形成的至少一个接触孔，其中所述至少一个接触通孔接触所述至少一个接触区域。

公开(公告)号：US20150279941A1

公开(公告)日：2015-10-01

申请号：US14719974

申请日：2015-05-22

Applicant: Infineon Technologies AG

Inventor： Rudolf Berger ,  Hermann Gruber ,  Wolfgang Lehnert ,  Guenther Ruhl ,  Raimund Foerg ,  Anton Mauder ,  Hans-Joachim Schulze

IPC: H01L29/161 ,  H01L29/04

CPC classification number: H01L21/76251 ,  H01L21/02002 ,  H01L21/0237 ,  H01L21/0243 ,  H01L21/02527 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/7624 ,  H01L29/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161

Abstract: A composite wafer including a carrier substrate having a graphite core and a monocrystalline semiconductor substrate or layer attached to the carrier substrate and a corresponding method for manufacturing such a composite wafer is provided.

Abstract translation: 提供了一种复合晶片，其包括具有石墨芯和附着于载体基板的单晶半导体衬底或层的载体衬底和用于制造这种复合晶片的相应方法。

公开(公告)号：US09123828B2

公开(公告)日：2015-09-01

申请号：US14080098

申请日：2013-11-14

Applicant: Infineon Technologies AG

Inventor： Holger Hüsken ,  Anton Mauder ,  Hans-Joachim Schulze ,  Wolfgang Rösner ,  Holger Schulze

IPC: H01L21/28 ,  H01L29/872 ,  H01L29/66 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/32 ,  H01L29/36 ,  H01L29/417 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/868

Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.

Abstract translation: 半导体器件包括在半导体器件的半导体衬底和邻近半导体衬底设置的导电结构之间的至少一个欧姆接触区域。 此外，半导体器件包括半导体器件的半导体衬底和导电结构之间的至少一个肖特基接触区域。 所述至少一个欧姆接触区域布置成与所述至少一个肖特基接触区域相邻。 半导体衬底包括邻近导电结构设置的第一掺杂层。 在至少一个欧姆接触区域的区域中，第一掺杂层的表面区域的平均掺杂浓度与至少一个肖特基接触区域的区域中的第一掺杂层的表面区域的平均掺杂浓度不同 少于10％。

公开(公告)号：US09048095B2

公开(公告)日：2015-06-02

申请号：US14470996

申请日：2014-08-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz Hirler ,  Hans Peter Felsl ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/302 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/02576 ,  H01L21/302 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.

Abstract translation: 一种制造半导体器件的方法包括：通过形成漂移区来形成半导体二极管，在漂移区中或漂移区上形成第一导电类型的第一半导体区域，并通过第一表面的第一表面电耦合第一半导体区域到第一端子 半导体本体，将沟槽蚀刻到半导体本体中，以及在沟槽中形成第二导电类型的沟道区，并且经由半导体本体的第一表面将沟道区电耦合到第一端。 沟道区的第一侧邻接第一半导体区。

公开(公告)号：US20240363700A1

公开(公告)日：2024-10-31

申请号：US18140782

申请日：2023-04-28

Applicant: Infineon Technologies AG

Inventor： Lars Mueller-Meskamp ,  Ralf Rudolf ,  Anton Mauder ,  Annett Winzer ,  Dirk Priefert ,  Christian Schippel ,  Thomas Kuenzig

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L29/404 ,  H01L29/7816

Abstract: A semiconductor device includes: a silicon layer having an electrically insulated backside and a thickness in a range of 10 μm to 200 μm between a frontside of the silicon layer and the electrically insulated backside; a high voltage region and a low voltage region formed in the silicon layer and laterally spaced apart from one another; and a first field plate structure extending from the frontside into the silicon layer. The first field plate structure includes a field plate laterally separated from the silicon layer by a dielectric material and/or a pn junction.

公开(公告)号：US11728420B2

公开(公告)日：2023-08-15

申请号：US17374323

申请日：2021-07-13

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Hans-Juergen Thees

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7804 ,  H01L29/41741 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device includes: a semiconductor body with a drift region; a plurality of trenches, wherein two adjacent trenches laterally confine a mesa of the semiconductor body. Each trench extends along a vertical direction and includes a trench electrode, and has a trench width along a first lateral direction and a trench length along a second lateral direction perpendicular to the first lateral direction, the trench length amounting to at least five times the trench width. The device further includes: a semiconductor body region of a second conductivity type in the mesa; a source region in the mesa; an insulation layer above and/or on the source region; a contact plug that extends at least from an upper surface of the insulation layer along the vertical direction so as to contact both the source region and the semiconductor body region.