公开(公告)号：US06294450B1

公开(公告)日：2001-09-25

申请号：US09516989

申请日：2000-03-01

申请人： Yong Chen ,  R. Stanley Williams

发明人： Yong Chen ,  R. Stanley Williams

IPC分类号： H01L2144

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F7/0002 ,  H01L21/3213 ,  H01L21/76838 ,  Y10S977/887

摘要： A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires. The nanoscale platen thus comprises a plurality of alternating layers of the two dissimilar materials, with the layers of one material etched relative the layers of the other material to form indentations of the one material. The platen is then oriented such that the indentations are parallel to a surface to be imprinted.

公开(公告)号：US6096160A

公开(公告)日：2000-08-01

申请号：US840325

申请日：1997-04-16

申请人： Shingo Kadomura

发明人： Shingo Kadomura

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  C23F1/02

CPC分类号： H01J37/321 ,  C23F4/00 ,  H01J37/3211 ,  H01J37/32422 ,  H01L21/3213 ,  H01J2237/3345 ,  H01J2237/3346

摘要： Controlling ion/radical ratio and monoatomic/polyatomic radical ratio in a process plasma provides improved processing performance during inductively-coupled plasma and/or helicon wave plasma processing of substrate materials. In a plasma processing method employing inductively coupled plasma, high frequency current to a high frequency antenna is intermittently supplied in a controlled manner to control the state of gas dissociation to promote formation of polyatomic radicals. In a plasma processing method employing helicon wave plasma, current supplied to a magnetic field generator is intermittently supplied in a controlled manner to promote formation of ions. In a preferred method, both the high frequency current and magnetic field generating current are varied in a controlled manner to provide a variable plasma composition, i.e., radical rich plasma or ion-rich plasma, as desired, for improved plasma processing, especially improved selective anisotropic dry etching at high etch rate.

摘要翻译： 处理等离子体中的离子/自由基比例和单原子/多原子自由基比率的控制在衬底材料的电感耦合等离子体和/或螺旋波等离子体处理中提供了改进的处理性能。 在使用电感耦合等离子体的等离子体处理方法中，以受控的方式间歇地供给高频天线的高频电流，以控制气体解离的状态，促进多原子团的形成。 在采用螺旋波等离子体的等离子体处理方法中，以受控的方式间歇地供给提供给磁场发生器的电流，以促进离子的形成。 在优选的方法中，高频电流和磁场发生电流都以受控的方式变化，以提供可变的等离子体组成，即根据需要的富自由基富集的等离子体或离子富集等离子体，用于改进的等离子体处理，特别是改进的选择性 以高蚀刻速率进行各向异性干蚀刻。

公开(公告)号：US5775980A

公开(公告)日：1998-07-07

申请号：US743044

申请日：1996-11-04

申请人： Yasutaka Sasaki ,  Mie Matsuo ,  Rempei Nakata ,  Junichi Wada ,  Nobuo Hayasaka ,  Hiroyuki Yano ,  Haruo Okano

发明人： Yasutaka Sasaki ,  Mie Matsuo ,  Rempei Nakata ,  Junichi Wada ,  Nobuo Hayasaka ,  Hiroyuki Yano ,  Haruo Okano

IPC分类号： B24B37/015 ,  B24B49/14 ,  B24B57/02 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  B24B5/00

CPC分类号： B24B37/015 ,  B24B57/02 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/3213 ,  H01L21/7684

摘要： This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.

摘要翻译： 本发明提供了一种抛光方法，包括以下步骤：在其表面上具有凹陷部分的基底上形成待研磨的膜，以便至少填充凹部，并且通过在凹部中选择性地将被抛光的膜留在后面 通过使用含有研磨粒子和溶剂的研磨剂，pH为7.5以上来研磨该膜。 本发明还提供了一种抛光装置，其包括：用于存储抛光剂的抛光剂储存容器，用于抛光待抛光对象物的转盘，用于将抛光剂从抛光剂储存容器供应到转台上的抛光剂供给管， 抛光对象保持夹具，用于保持待抛光对象物，使被处理物体的表面与转盘相对;抛光剂供给管温度调节单元，连接到抛光剂供应管，用于调节抛光温度 代理商

公开(公告)号：US5693557A

公开(公告)日：1997-12-02

申请号：US590086

申请日：1996-01-24

申请人： Shuji Hirao ,  Hisashi Ogawa ,  Yuka Terai ,  Mitsuru Sekiguchi ,  Masanori Fukumoto ,  Isao Miyanaga

发明人： Shuji Hirao ,  Hisashi Ogawa ,  Yuka Terai ,  Mitsuru Sekiguchi ,  Masanori Fukumoto ,  Isao Miyanaga

IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/70

CPC分类号： H01L28/84 ,  H01L21/3213 ,  H01L21/32131 ,  H01L21/76838 ,  Y10S148/014 ,  Y10S438/964

摘要： A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

公开(公告)号：US5662819A

公开(公告)日：1997-09-02

申请号：US383227

申请日：1995-02-03

申请人： Shingo Kadomura

发明人： Shingo Kadomura

IPC分类号： C23F4/00 ,  H01J37/32 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  B44C1/22 ,  C03C15/00 ,  C03C25/06 ,  C23F1/00

CPC分类号： H01J37/321 ,  C23F4/00 ,  H01J37/3211 ,  H01J37/32422 ,  H01L21/3213 ,  H01J2237/3345 ,  H01J2237/3346

摘要： Controlling ion/radical ratio and monoatomic/polyatomic radical ratio in a process plasma provides improved processing performance during inductively-coupled plasma and/or helicon wave plasma processing of substrate materials. In a plasma processing method employing inductively coupled plasma, high frequency current to a high frequency antenna is intermittently supplied in a controlled manner to control the state of gas dissociation to promote formation of polyatomic radicals. In a plasma processing method employing helicon wave plasma, current supplied to a magnetic field generator is intermittently supplied in a controlled manner to promote formation of ions. In a preferred method both the high frequency current and magnetic field generating current are varied in a controlled manner to provide a variable plasma composition, i.e., radical rich plasma or ion-rich plasma, as desired, for improved plasma processing especially improved selective anisotropic dry etching at high etch rate.

摘要翻译： 处理等离子体中的离子/自由基比例和单原子/多原子自由基比率的控制在衬底材料的电感耦合等离子体和/或螺旋波等离子体处理中提供了改进的处理性能。 在使用电感耦合等离子体的等离子体处理方法中，以受控的方式间歇地供给高频天线的高频电流，以控制气体解离的状态，促进多原子团的形成。 在采用螺旋波等离子体的等离子体处理方法中，以受控的方式间歇地供给提供给磁场发生器的电流，以促进离子的形成。 在优选的方法中，高频电流和磁场发生电流以受控的方式变化，以提供可变的等离子体组成，即根据需要的富自由基富集等离子体或富离子的等离子体，用于改进的等离子体处理，特别是改进的选择性各向异性干燥 以高蚀刻速率蚀刻。

公开(公告)号：US5598317A

公开(公告)日：1997-01-28

申请号：US597785

申请日：1996-02-07

申请人： Ciaran Hanrahan ,  Andrew P. Stack

发明人： Ciaran Hanrahan ,  Andrew P. Stack

IPC分类号： H01L21/02 ,  H01L21/3105 ,  H01L21/3213 ,  H01G4/005 ,  H01G4/06

CPC分类号： H01L28/10 ,  H01L21/3105 ,  H01L21/3213 ,  Y10T29/435

摘要： A semiconductor capacitor used to test for contaminants in a fabrication line is created by: forming a layer of insulating material on a semiconductor substrate, forming a layer of conductive thin film on the layer of insulating material, and laser patterning an area of the conductive thin film. Laser patterning is performed by applying the laser along the outer boundary of the area to be patterned to energetically remove the conductive thin film along this boundary.

摘要翻译： 用于测试制造线中的污染物的半导体电容器是通过在半导体衬底上形成绝缘材料层，在绝缘材料层上形成导电薄膜层，以及激光构图导电薄膜 电影。 通过沿着要构图的区域的外边界应用激光来沿着该边界能量地去除导电薄膜来进行激光图案化。

公开(公告)号：US20190189459A1

公开(公告)日：2019-06-20

申请号：US16221456

申请日：2018-12-15

申请人： Guangdong University of Technology

发明人： Yun CHEN ,  Xin CHEN ,  Jian GAO ,  Zhengping WANG ,  Haidong YANG

IPC分类号： H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67 ,  G01F23/64

CPC分类号： H01L21/30612 ,  G01F23/64 ,  H01L21/3081 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/67063

摘要： Disclosed is a processing device for the third generation semiconductor materials. The device includes a reaction device, an operating platform and a support device. A reaction chamber is located inside the reaction device and the upper and lower ends of the reaction device are covered with an upper cover and a lower cover, respectively. An etching solution injection port and an etching solution discharge port are provided at the side wall of the reaction chamber. A stirring excitation coil, a plurality of conducting rods, a plurality of heating rods, a plurality of sealing rings and a workpiece are provided inside of the reaction chamber. The stirring excitation coil is mounted just under the upper cover; the conducting rods and the heating rods are respectively mounted in a circumferentially symmetrical manner in an inner wall of the reaction chamber.

公开(公告)号：US20180350960A1

公开(公告)日：2018-12-06

申请号：US15987912

申请日：2018-05-24

申请人： Fuji Electric Co., Ltd.

发明人： Tatsuya NAITO

IPC分类号： H01L29/739 ,  H01L29/78 ,  H01L29/423 ,  H01L23/00

CPC分类号： H01L29/7397 ,  G01R31/2637 ,  G01R31/2644 ,  H01L21/221 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28035 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/302 ,  H01L21/3213 ,  H01L21/3223 ,  H01L21/324 ,  H01L21/743 ,  H01L21/7685 ,  H01L22/30 ,  H01L22/32 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53271 ,  H01L23/535 ,  H01L27/0727 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/32 ,  H01L29/401 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66303 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/861

摘要： Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

公开(公告)号：US20180294378A1

公开(公告)日：2018-10-11

申请号：US16006765

申请日：2018-06-12

申请人： OSRAM Opto Semiconductors GmbH

发明人： Isabel OTTO ,  Alexander F. PFEUFFER ,  Dominik SCHOLZ

IPC分类号： H01L33/08 ,  H01L27/15 ,  H01L33/38 ,  H01L21/3065 ,  H01L33/00 ,  H01L31/12 ,  H01L21/28 ,  H01L21/461 ,  H01L21/3213 ,  H01L21/311 ,  H01L25/16

CPC分类号： H01L33/08 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/461 ,  H01L25/167 ,  H01L27/156 ,  H01L31/12 ,  H01L33/00 ,  H01L33/38 ,  H01L2933/0016 ,  H01L2933/0033

摘要： A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having—a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c),—an active layer (23), and—a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein—the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that—the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and—the first contact layer (41) and the second contact layer (42) run parallel to each other.

公开(公告)号：US10008563B2

公开(公告)日：2018-06-26

申请号：US15402929

申请日：2017-01-10

申请人： International Business Machines Corporation

发明人： Praneet Adusumilli ,  Alexander Reznicek ,  Oscar Van der Straten ,  Chih-Chao Yang

IPC分类号： H01L29/06 ,  H01L21/768 ,  H01L21/31 ,  H01L21/265 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/764

CPC分类号： H01L29/0649 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/31 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

摘要： Aspects of the invention are directed to a method for forming a semiconductor device. A dielectric layer is formed on a semiconductor substrate. Subsequently, a metallic contact is formed in the dielectric layer such that it lands on the semiconductor substrate. A masking layer comprising a block copolymer is then formed on the dielectric layer. This block copolymer is caused to separate into two phases. One of the two phases is selectively removed to leave a patterned masking layer. The patterned masking layer is used to etch the dielectric layer. The patterned air gaps reduce the interconnect capacitance of the semiconductor device while leaving the dielectric layer with enough mechanical strength to serve as a middle-of-line dielectric.