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    Transmit driver architecture
    112.
    发明授权
    Transmit driver architecture 有权

    公开(公告)号：US11728835B2

    公开(公告)日：2023-08-15

    申请号：US17463897

    申请日：2021-09-01

    Applicant: RAMBUS INC.

    Inventor： Kamran Farzan

    IPC: H04B1/04 ,  H04B1/00

    CPC classification number: H04B1/0483 ,  H04B1/0028

    Abstract: An apparatus including a signal generation circuitry to provide a stream of digital signals carrying data. The apparatus includes a storage circuitry to provide a plurality of transmit levels corresponding to respective predetermined equalization levels; selection circuitry to select a transmit level from among the plurality of transmit levels based on the digital signals carrying data. Each of the plurality of transmit levels is a respective input signal to the selection circuitry. The apparatus includes a digital-to-analog converter (DAC) circuitry configured to receive the selected transmit level and convert the selected transmit level to an analog signal of the selected transmit level.

    Memory systems and methods for improved power management
    113.
    发明授权
    Memory systems and methods for improved power management 有权

    公开(公告)号：US11710520B2

    公开(公告)日：2023-07-25

    申请号：US17702475

    申请日：2022-03-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C8/12 ,  G11C11/4093 ,  G11C5/04 ,  G11C5/06 ,  G11C7/22

    CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C5/063 ,  G11C7/22 ,  G11C8/12

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Protocol For Refresh Between A Memory Controller And A Memory Device
    115.
    发明公开
    Protocol For Refresh Between A Memory Controller And A Memory Device 审中-公开

    公开(公告)号：US20230223067A1

    公开(公告)日：2023-07-13

    申请号：US18078934

    申请日：2022-12-10

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G11C11/406 ,  G06F13/16

    CPC classification number: G11C11/40611 ,  G06F13/1636 ,  G11C11/40615 ,  G11C11/406 ,  G11C11/40618 ,  Y02D10/00 ,  G11C2211/4067

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

    Offset calibration for successive approximation register analog to digital converter
    119.
    发明授权
    Offset calibration for successive approximation register analog to digital converter 有权

    公开(公告)号：US11671108B2

    公开(公告)日：2023-06-06

    申请号：US17728607

    申请日：2022-04-25

    Applicant: Rambus Inc.

    Inventor： Kenneth C. Dyer ,  Marcus Van Ierssel

    IPC: H03M1/10 ,  H03M1/06 ,  H03M1/46

    CPC classification number: H03M1/1023 ,  H03M1/0639 ,  H03M1/46

    Abstract: Disclosed is a successive approximation register (SAR) analog to digital converter (ADC) that uses two or more comparators. This allows the output of one comparator to be latched while the other comparators are comparing and switching. Statistical measures are used to correct the offsets of one or more of the comparators. If a statistically significant mismatch in the number of 1's and 0's occurs in a subset of the bits, adjustments to the offsets of one or more of the comparators are made until there is roughly an equal number of 1 and 0 values. This can reduce or eliminate the need for dedicated offset correction cycles.

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