公开(公告)号：US09343675B2

公开(公告)日：2016-05-17

申请号：US14506193

申请日：2014-10-03

Applicant: Intermolecular Inc.

Inventor： Tony P. Chiang

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79

Abstract: Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Abstract translation: 提供多个非易失性存储器元件。 多个非易失性存储器元件包含多个层。 每个层可以基于不同的双稳态材料。 双稳态材料可以是电阻式开关材料，例如电阻式开关金属氧化物。 可选导体层和电流导向元件可以与双稳电阻开关金属氧化物层串联连接。

公开(公告)号：US09276211B2

公开(公告)日：2016-03-01

申请号：US14721640

申请日：2015-05-26

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak ,  Tony P. Chiang ,  Pragati Kumar ,  Michael Miller

IPC: H01L45/00 ,  H01L47/00 ,  H01L29/861 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

公开(公告)号：US09269567B2

公开(公告)日：2016-02-23

申请号：US14109622

申请日：2013-12-17

Applicant: Intermolecular Inc.

Inventor： Chien-Lan Hsueh ,  Chen-An Chen ,  Tony P. Chiang ,  Martin Romero ,  James Tsung

IPC: C23C16/455 ,  H01L21/02

CPC classification number: H01L21/02271 ,  C23C16/45548 ,  C23C16/45561 ,  C23C16/45565 ,  C23C16/45574

Abstract: Apparatus for high productivity combinatorial (HPC) processing of semiconductor substrates and HPC methods are described. An apparatus includes a showerhead and two or more pressure-controlled one-way valves connected to the showerhead and used for controlling flow of different processing gases into the showerhead. The pressure-controlled one-way valves are not externally controlled by any control systems. Instead, these valves open and close in response to preset conditions, such as pressure differentials and/or flow differentials. One example of such pressure-controlled one-way valves is a check valve. These valves generally allow the flow only in one direction, i.e., into the showerhead. Furthermore, lack of external controls and specific mechanical designs allow positioning these pressure-controlled one-way valves in close proximity to the showerhead thereby reducing the dead volume between the valves and the showerhead and also operating these valves at high temperatures.

Abstract translation: 描述了用于半导体衬底和HPC方法的高生产率组合（HPC）处理的装置。 一种装置包括一个淋浴喷头和两个或多个压力控制单向阀，连接到喷头并用于控制不同处理气体进入喷头的流量。 压力控制单向阀不受任何控制系统的外部控制。 相反，这些阀响应预设条件（例如压力差和/或流量差）打开和关闭。 这种压力控制单向阀的一个例子是止回阀。 这些阀通常仅在一个方向上流动，即进入喷头。 此外，缺乏外部控制和特定的机械设计允许将这些压力控制的单向阀定位在靠近喷头处，从而减小阀和喷头之间的死体积并且还在高温下操作这些阀。

公开(公告)号：US09245744B2

公开(公告)日：2016-01-26

申请号：US14253712

申请日：2014-04-15

Applicant: Intermolecular, Inc.

Inventor： Sunil Shanker ,  Tony P. Chiang ,  Chi-I Lang

IPC: C23C16/50 ,  C23C16/509 ,  H01L21/02 ,  C23C16/44 ,  C23C16/455 ,  H01J37/32 ,  C23C16/02 ,  C23C16/458 ,  H01L21/67 ,  H01L21/3065

CPC classification number: H01L21/02274 ,  C23C16/0227 ,  C23C16/44 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/45536 ,  C23C16/45548 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/4586 ,  C23C16/509 ,  C23C16/5096 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32532 ,  H01J37/32541 ,  H01J37/32568 ,  H01J37/32715 ,  H01J37/32779 ,  H01L21/3065 ,  H01L21/67069

Abstract: According to various embodiments of the disclosure, an apparatus and method for enhanced deposition and etch techniques is described, including a pedestal, the pedestal having at least two electrodes embedded in the pedestal, a showerhead above the pedestal, a plasma gas source connected to the showerhead, wherein the showerhead is configured to deliver plasma gas to a processing region between the showerhead and the substrate and a power source operably connected to the showerhead and the at least two electrodes with plasma being substantially contained in an area which corresponds with one electrode of the at least two electrodes.

Abstract translation: 根据本公开的各种实施例，描述了一种用于增强沉积和蚀刻技术的装置和方法，包括基座，具有至少两个嵌入基座的电极的基座，基座上方的喷头，连接到基座的等离子体气体源 淋浴头，其中所述喷头被构造成将等离子体气体输送到所述喷头和所述基板之间的处理区域，以及电源，其可操作地连接到所述喷头和所述至少两个电极，其中等离子体基本上包含在对应于 所述至少两个电极。

公开(公告)号：US09176181B2

公开(公告)日：2015-11-03

申请号：US13971325

申请日：2013-08-20

Applicant: Intermolecular, Inc.

Inventor： Yun Wang ,  Tony P. Chiang ,  Chi-I Lang

IPC: G01R31/26 ,  G01N21/55 ,  H02S50/10

CPC classification number: G01R31/26 ,  G01N21/55 ,  G01R31/2607 ,  H02S50/10

Abstract: Measuring current-voltage (I-V) characteristics of a solar cell using a lamp that emits light, a substrate that includes a plurality of solar cells, a positive electrode attached to the solar cells, and a negative electrode peripherally deposited around each of the solar cells and connected to a common ground, an articulation platform coupled to the substrate, a multi-probe switching matrix or a Z-stage device, a programmable switch box coupled to the multi-probe switching matrix or Z-stage device and selectively articulating the probes by raising the probes until in contact with at least one of the positive electrode and the negative electrode and lowering the probes until contact is lost with at least one of the positive electrode and the negative electrode, a source meter coupled to the programmable switch box and measuring the I-V characteristics of the substrate.

Abstract translation: 使用发光灯的太阳能电池测量电流 - 电压（IV）特性，包括多个太阳能电池的基板，附着到太阳能电池的正电极和周围沉积在每个太阳能电池周围的负电极 并且连接到公共接地，耦合到衬底的关节式平台，多探针开关矩阵或Z级装置，耦合到多探针开关矩阵或Z级装置的可编程开关盒，并且选择性地将探针 通过将探针升高直到与正电极和负电极中的至少一个接触并且降低探针，直到与正电极和负电极中的至少一个接触而丢失，源计量器耦合到可编程开关盒和 测量衬底的IV特性。

公开(公告)号：US09130165B2

公开(公告)日：2015-09-08

申请号：US14506298

申请日：2014-10-03

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik

IPC: H01L47/00 ,  H01L45/00 ,  C23C16/40 ,  C23C16/455 ,  H01L21/02 ,  H01L27/24

CPC classification number: H01L45/145 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/0228 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.

Abstract translation: 本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。 金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。 设置在金属氧化物层之间的界面有助于氧空位移动。 在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对齐的晶粒界面，其包含平行于电极界面延伸的许多晶界。 因此，氧空缺在切换期间被捕获和释放，而空位明显损失。 因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

公开(公告)号：US09087864B2

公开(公告)日：2015-07-21

申请号：US14135307

申请日：2013-12-19

Applicant: Intermolecular, Inc.

Inventor： Chen-An Chen ,  Tony P. Chiang ,  Frank Greer ,  Martin Romero ,  James Tsung

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/677 ,  H01L21/02

CPC classification number: H01L21/02271 ,  C23C16/04 ,  C23C16/45529 ,  C23C16/45544 ,  C23C16/45574 ,  C23C16/4584 ,  C23C16/54 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/6719 ,  H01L21/67207

Abstract: In some embodiments, apparatus are provided that provide for flexible processing in high productivity combinatorial (HPC) system. The apparatus allow for interchangeable functionality that includes deposition, plasma treatment, ion beam treatment, in-situ annealing, and in-situ metrology. The apparatus are designed so that the functionality may be integrated within a single processing chamber for enhanced flexibility.

Abstract translation: 在一些实施例中，提供了在高生产率组合（HPC）系统中提供灵活处理的装置。 该装置允许可互换的功能，包括沉积，等离子体处理，离子束处理，原位退火和原位计量。 该设备被设计为使得功能可以集成在单个处理室内以增强灵活性。

公开(公告)号：US09076716B2

公开(公告)日：2015-07-07

申请号：US14077137

申请日：2013-11-11

Applicant: Intermolecular, Inc.

Inventor： Thomas R. Boussie ,  Tony P. Chiang ,  Alexander Gorer ,  David E. Lazovsky

IPC: C40B50/00 ,  H01L21/66 ,  C23C14/54 ,  C23C16/52 ,  H01L21/67 ,  H01L21/768

CPC classification number: H01L21/67011 ,  C23C14/54 ,  C23C16/4412 ,  C23C16/45544 ,  C23C16/4557 ,  C23C16/45578 ,  C23C16/4583 ,  C23C16/46 ,  C23C16/52 ,  H01J37/32449 ,  H01J37/32513 ,  H01J37/32724 ,  H01J2237/166 ,  H01J2237/20228 ,  H01J2237/20235 ,  H01L21/6715 ,  H01L21/76849 ,  H01L22/20 ,  H01L2924/0002 ,  Y10S438/907 ,  Y10S438/913 ,  Y10T137/8593 ,  H01L2924/00

Abstract: The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate.

Abstract translation: 本发明提供了用于基板区域的离散化，组合处理的方法和系统，例如用于集成电路制造中使用的新材料，工艺和工艺顺序集成方案的发现，实现，优化和鉴定。 通过将材料输送到衬底或修改衬底的区域来处理其上具有差分处理区域阵列的衬底。

公开(公告)号：US20150176122A1

公开(公告)日：2015-06-25

申请号：US14136384

申请日：2013-12-20

Applicant: Intermolecular Inc.

Inventor： Chien-Lan Hsueh ,  Tony P. Chiang ,  Randall J. Higuchi ,  Kurt Pang

IPC: C23C16/44

CPC classification number: C23C16/44 ,  C23C16/308 ,  C23C16/34 ,  C23C16/45527 ,  Y10T428/24355

Abstract: Ternary oxides, nitrides and oxynitrides of the form (a)(b)OxNy are formed by ALD or CVD when the reaction temperature ranges of the (a) precursor and the (b) precursor do not overlap. Chemically-reacted sub-layers, e.g., (a)OxNy, are formed by reacting the lower-temperature precursor with O and/or N at a temperature within its reaction range. Physisorbed sub-layers (e.g., (b) or (b)+ligand) are formed between the chemically-reacted sub-layers by allowing the higher-temperature precursor to physically adsorb to the low-temperature surface. When the desired sub-layers are formed, the substrate is heated to a temperature at which the higher-temperature precursor reacts (optionally in the presence of more O and/or N) to form (a)(b)OxNy. Quarternary and more complex compounds can be similarly formed.

Abstract translation: （a）（a）（b）的三元氧化物，氮化物和氮氧化物当（a）前体和（b）前体的反应温度范围不重叠时，通过ALD或CVD形成OxNy。 化学反应的亚层，例如，（a）OxNy是通过在其反应范围内的温度下使低温前体与O和/或N反应形成的。 通过使高温前体物理吸附到低温表面，在化学反应的子层之间形成物理吸附的子层（例如，（b）或（b）+配体））。 当形成所需的子层时，将基底加热至较高温度前体反应的温度（任选地在更多的O和/或N的存在下）以形成（a）（b）OxNy。 可以类似地形成四元和更复杂的化合物。

公开(公告)号：US09054032B2

公开(公告)日：2015-06-09

申请号：US14325580

申请日：2014-07-08

Applicant: Intermolecular Inc.

Inventor： Dipankar Pramanik ,  Tony P. Chiang ,  David E Lazovsky

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L45/1658 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1683

Abstract: An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Abstract translation: 本发明的实施例提出了一种嵌入式电阻式存储单元，其包括沉积层的第一堆叠，沉积层的第二堆叠，设置在第一堆叠的第一部分下方的第一电极和设置在第二堆叠下的第二电极的第二电极 第一堆叠的部分并且从第一堆叠的第二部分下方延伸到第二堆叠下方。 第二电极设置在嵌入式电阻式存储单元内靠近第一电极。 第一堆沉积层包括介电层，设置在电介质层上方的高k电介质层和设置在高k电介质层上方的金属层。 第二层沉积层包括与包含在第一堆叠中的高k电介质层同时形成的高k电介质层，以及设置在高k电介质层上方的金属层。