公开(公告)号：US08021924B2

公开(公告)日：2011-09-20

申请号：US12892907

申请日：2010-09-28

申请人： Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Byung Joon Han ,  Kambhampati Ramakrishna ,  Seng Guan Chow

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L31/0203 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for fabricating an encapsulant cavity integrated circuit package system includes: forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

摘要翻译： 一种用于制造密封腔的集成电路封装系统的方法，包括：形成第一集成电路封装，其具有具有封装腔和反射器的倒置底端，并且将组件附着在封装腔中的插入件上。

公开(公告)号：US20110127678A1

公开(公告)日：2011-06-02

申请号：US13023293

申请日：2011-02-08

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Seung Uk Yoon ,  Jong-Woo Ha

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan ,  Seung Uk Yoon ,  Jong-Woo Ha

IPC分类号： H01L23/50

CPC分类号： H01L24/19 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2224/82 ,  H01L2924/00

摘要： An integrated circuit packaging system includes: an integrated circuit device; a conductive post adjacent the integrated circuit device, the conductive post with a contact surface having characteristics of a shaped platform removed; and an encapsulant around the conductive post and the integrated circuit device with the conductive post extending through the encapsulant and each end of the conductive post exposed from the encapsulant.

摘要翻译： 一种集成电路封装系统，包括：集成电路器件; 邻近集成电路器件的导电柱，具有去除成形平台特征的接触表面的导电柱; 以及围绕导电柱和集成电路器件的密封剂，其中导电柱延伸穿过密封剂并且从密封剂暴露出的导电柱的每个端部。

公开(公告)号：US07842542B2

公开(公告)日：2010-11-30

申请号：US12266313

申请日：2008-11-06

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each having a lead frame interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the lead frame interconnect structure and encapsulant. The package interconnect structure and lead frame interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the lead frame interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the lead frame interconnect structure.

摘要翻译： 嵌入式半导体管芯封装通过使用粘合剂将框架载体安装到临时载体上而制成。 框架载体包括每个具有围绕空腔的引线框架互连结构的管芯安装位置。 半导体管芯设置在每个腔中。 将密封剂沉积在模具上的空腔中。 封装互连结构形成在引线框架互连结构和密封剂上。 封装互连结构和引线框架互连结构电连接到管芯。 帧载体被分成单独的嵌入式芯片封装。 半导体管芯可以垂直堆叠或并排放置在腔内。 嵌入式管芯封装可以通过引线框架互连结构堆叠并电互连。 半导体器件可以安装到嵌入式裸片封装并且通过引线框架互连结构电连接到管芯。

公开(公告)号：US20100289142A1

公开(公告)日：2010-11-18

申请号：US12777615

申请日：2010-05-11

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/28 ,  H01L21/60

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an interconnect to the substrate; encapsulating the interconnect with an encapsulation leaving a portion of the interconnect not encapsulated; attaching a joint to the interconnect and simultaneously creating a coined-surface of the interconnect contacting the joint; and attaching an integrated circuit to the substrate.

摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 将互连件连接到所述基板上; 用封装封装互连，留下未封装的互连部分; 将接头附接到所述互连件并且同时产生接触所述接头的所述互连件的模制表面; 以及将集成电路附接到所述基板。

公开(公告)号：US20100289134A1

公开(公告)日：2010-11-18

申请号：US12777415

申请日：2010-05-11

申请人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Youngcheol Kim

发明人： Seng Guan Chow ,  Il Kwon Shim ,  Heap Hoe Kuan ,  Youngcheol Kim

IPC分类号： H01L23/31 ,  H01L21/56 ,  H01L23/488

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling stacking interconnects on the component side; and forming an integrated circuit receptacle, for receiving an integrated circuit device, by molding a reinforced encapsulant on the component side and exposing a portion of the stacking interconnects.

摘要翻译： 一种集成电路封装系统的制造方法，包括：制造具有元件侧和系统侧的基底封装基板; 在组件侧耦合堆叠互连; 以及形成用于接收集成电路器件的集成电路插座，通过在组件侧上模制增强的密封剂并暴露所述堆叠互连的一部分。

公开(公告)号：US07746656B2

公开(公告)日：2010-06-29

申请号：US11383407

申请日：2006-05-15

申请人： Il Kwon Shim ,  Byung Joon Han ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Byung Joon Han ,  Seng Guan Chow

IPC分类号： H05K7/00

CPC分类号： H05K1/141 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/85

摘要： An offset integrated circuit package-on-package stacking system is provided including providing a base substrate, providing an array of contact pads on the base substrate, mounting an active component and an optional passive component on the base substrate, injecting a mold cap on the base substrate, mounting an offset package on the base substrate and the mold cap, and singulating a package-on-package from the base substrate.

摘要翻译： 提供了一种偏移集成电路封装堆叠堆叠系统，包括提供基底基板，在基底基板上提供接触焊盘的阵列，将有源部件和可选的无源部件安装在基底基板上，将模具帽 在基底基板和模具盖上安装偏移封装，以及从基底基板上单独封装封装。

公开(公告)号：US20100140771A1

公开(公告)日：2010-06-10

申请号：US12329458

申请日：2008-12-05

申请人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

发明人： Rui Huang ,  Il Kwon Shim ,  Seng Guan Chow ,  Heap Hoe Kuan

IPC分类号： H01L21/50 ,  H01L23/538

CPC分类号： H01L23/49811 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

摘要翻译： 使用包括基板和多个导电柱的预制柱载体制成半导体封装。 胶片密封剂设置在柱载体的基板上并且在导电柱周围。 半导体管芯安装到临时载体上。 将载体和临时载体压在一起以将半导体管芯嵌入膜密封剂中。 半导体管芯设置在膜密封剂中的导电柱之间。 卸载载体的临时载体和基板。 在膜密封剂的第一侧上形成第一电路堆积层。 第一电路堆积层电连接到导电柱。 第二电路堆积层形成在与第一侧相对的膜密封剂的第二侧上。 第二电路堆积层电连接到导电柱。

公开(公告)号：US07732907B2

公开(公告)日：2010-06-08

申请号：US11421051

申请日：2006-05-30

申请人： Byung Joon Han ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Byung Joon Han ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/36 ,  H01L23/552 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/162 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K2201/042 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10446 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system including a plurality of substrates and a plurality of semiconductor devices formed on each of the substrates. An edge connection system is provided and an electrical edge connector on each of the substrates is for attachment to the edge connection system. A vertically stacked configuration of the substrates is formed by attaching the substrates to the edge connection system.

摘要翻译： 一种集成电路封装系统，包括多个基板和形成在每个基板上的多个半导体器件。 提供边缘连接系统，并且每个基板上的电气边缘连接器用于附接到边缘连接系统。 通过将基板附接到边缘连接系统来形成基板的垂直堆叠构造。

公开(公告)号：US20090321913A1

公开(公告)日：2009-12-31

申请号：US12146192

申请日：2008-06-25

申请人： Il Kwon Shim ,  Seng Guan Chow

发明人： Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L23/48

CPC分类号： H01L23/49541 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： An integrated circuit package system includes: forming a first locking terminal having a first terminal recess with a top portion of the first terminal recess narrower than a bottom portion of the first terminal recess; connecting an integrated circuit and the first locking terminal; and forming a package encapsulation over the integrated circuit and in the first locking terminal.

摘要翻译： 集成电路封装系统包括：形成具有第一端子凹槽的第一锁定端子，第一端子凹槽的顶部比第一端子凹槽的底部窄; 连接集成电路和第一锁定端子; 以及在所述集成电路和所述第一锁定端子中形成封装封装。

公开(公告)号：US20090309212A1

公开(公告)日：2009-12-17

申请号：US12481404

申请日：2009-06-09

申请人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

发明人： Il Kwon Shim ,  Seng Guan Chow ,  Yaojian Lin

IPC分类号： H01L23/482 ,  H01L21/50

CPC分类号： H01L23/562 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/48091 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.

摘要翻译： 通过在牺牲载体上形成第一导电层制成半导体器件。 在第一导电层上形成导电柱。 半导体管芯的有源表面安装在载体上。 密封剂沉积在半导体管芯上方并围绕导电柱。 去除载体和粘合剂层。 在半导体管芯的有源表面和密封剂的第一表面上形成应力消除绝缘层。 应力消除绝缘层在半导体管芯上方具有第一厚度，并且第二厚度小于密封剂上的第一厚度。 在应力消除绝缘层上形成第一互连结构。 在与第一互连结构相对的密封剂的第二表面上形成第二互连结构。 第一和第二互连结构通过导电柱电连接。