公开(公告)号：US20140061944A1

公开(公告)日：2014-03-06

申请号：US14079273

申请日：2013-11-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Jose Alvin Caparas ,  Glenn Omandam

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/315 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract translation: 半导体器件具有安装到载体上的半导体管芯。 第一密封剂沉积在半导体管芯和载体上。 加强支撑构件可以设置在半导体管芯周围的载体上。 在第一密封剂中形成多个通道或凹槽。 可以通过去除第一密封剂的一部分来形成凹部。 或者，凹部形成在具有多个延伸表面的追逐模具中。 可以将第二密封剂沉积到第一密封剂的凹部中。 移除载体并且在半导体管芯和第一密封剂上形成互连结构。 第一密封剂的厚度提供足够的刚度以减少翘曲，同时凹槽在形成互连结构期间提供应力释放。 去除第一密封剂和凹部的一部分以减小半导体器件的厚度。

公开(公告)号：US20140048906A1

公开(公告)日：2014-02-20

申请号：US14061244

申请日：2013-10-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/24155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a semiconductor package and an interposer disposed over the semiconductor package. The semiconductor package has a first semiconductor die and a modular interconnect unit disposed in a peripheral region around the first semiconductor die. A second semiconductor die is disposed over the interposer opposite the semiconductor package. An interconnect structure is formed between the interposer and the modular interconnect unit. The interconnect structure is a conductive pillar or stud bump. The modular interconnect unit has a core substrate and a plurality of vertical interconnects formed through the core substrate. A build-up interconnect structure is formed over the first semiconductor die and modular interconnect unit. The vertical interconnects of the modular interconnect unit are exposed by laser direct ablation. An underfill is deposited between the interposer and semiconductor package. A total thickness of the semiconductor package and build-up interconnect structure is less than 0.4 millimeters.

Abstract translation: 半导体器件具有设置在半导体封装之上的半导体封装和插入器。 半导体封装具有设置在第一半导体管芯周围的周边区域中的第一半导体管芯和模块化互连单元。 第二半导体管芯设置在与半导体封装件相对的插入件上。 在插入器和模块化互连单元之间形成互连结构。 互连结构是导电柱或螺柱凸块。 模块化互连单元具有芯基板和通过芯基板形成的多个垂直互连。 在第一半导体管芯和模块化互连单元上形成堆积互连结构。 模块化互连单元的垂直互连通过激光直接消融来暴露。 在内插器和半导体封装之间沉积底部填充物。 半导体封装和堆积互连结构的总厚度小于0.4毫米。

公开(公告)号：US20140027929A1

公开(公告)日：2014-01-30

申请号：US14043751

申请日：2013-10-01

Applicant: STATS ChipPAC. Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L23/00

CPC classification number: H01L24/06 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is deposited over the semiconductor die. A conductive micro via array is formed outside a footprint of the semiconductor die and over the semiconductor die and encapsulant. A first through-mold-hole (TMH) is formed including a step-through-hole structure through the encapsulant to expose the conductive micro via array. An insulating layer is formed over the semiconductor die and the encapsulant. A micro via array is formed through the insulating layer and outside the footprint of the semiconductor die. A conductive layer is formed over the insulating layer. A conductive ring is formed comprising the conductive micro via array. A second TMH is formed partially through the encapsulant to a recessed surface of the encapsulant. A third TMH is formed through the encapsulant and extending from the recessed surface of the encapsulant to the conductive micro via array.

Abstract translation: 半导体器件包括半导体管芯。 密封剂沉积在半导体管芯上。 导电微通孔阵列形成在半导体管芯的覆盖区之外并且在半导体管芯和密封剂之上。 形成第一通孔模具（TMH），其包括通过密封剂的通孔结构，以暴露导电微通孔阵列。 在半导体管芯和密封剂上形成绝缘层。 微通孔阵列通过绝缘层形成，并且在半导体管芯的覆盖区外部形成。 在绝缘层上形成导电层。 形成包括导电微通孔阵列的导电环。 第二TMH部分地通过密封剂形成到密封剂的凹陷表面。 通过密封剂形成第三TMH，并从密封剂的凹陷表面延伸到导电微通孔阵列。

公开(公告)号：US20130292851A1

公开(公告)日：2013-11-07

申请号：US13936099

申请日：2013-07-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Seung Uk Yoon

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/24225 ,  H01L2224/25171 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Abstract translation: 半导体器件具有在晶片的第一表面中形成有腔的TSV半导体晶片。 可以在晶片的第二表面中形成第二空腔。 多个半导体管芯安装在空腔内。 半导体管芯可以并排安装和/或堆叠在腔内。 可以通过模具形成导电TSV。 密封剂沉积在模具内的空腔内。 模具的CTE类似于密封剂的CTE。 在密封剂和晶片的第一表面上形成第一互连结构。 在密封剂和晶片的第二表面上形成第二互连结构。 第一和第二互连结构电连接到TSV晶片。 第二半导体管芯可以安装在第一互连结构上，并且封装在第二管芯上。

公开(公告)号：US20130264716A1

公开(公告)日：2013-10-10

申请号：US13910786

申请日：2013-06-05

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L23/52 ,  H01L21/56

CPC classification number: H01L23/52 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/64 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K3/20 ,  H05K3/284 ,  H05K3/4644 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding.

Abstract translation: 半导体器件具有衬底，形成在衬底上的第一钝化层和形成在衬底上的集成无源器件。 集成无源器件可以包括电感器，电容器和电阻器。 在该集成无源器件上形成第二钝化层。 系统组件被安装到第二钝化层并电连接到第二导电层。 在整合的无源器件上形成模具化合物。 模具化合物的热膨胀系数近似等于系统组分的热膨胀系数。 去除衬底。 将一个开口蚀刻到第一钝化层中，并且将焊料凸块沉积在第一钝化层中的开口上，以电连接到集成的无源器件。 可以在模制化合物或第一钝化层上形成金属层以进行屏蔽。

公开(公告)号：US20130207247A1

公开(公告)日：2013-08-15

申请号：US13845329

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Rui Huang ,  Yaojian Lin

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is made by forming an interconnect structure over a substrate. A semiconductor die is mounted to the interconnect structure. The semiconductor die is electrically connected to the interconnect structure. A ground pad is formed over the interconnect structure. An encapsulant is formed over the semiconductor die and interconnect structure. A shielding cage can be formed over the semiconductor die prior to forming the encapsulant. A shielding layer is formed over the encapsulant after forming the interconnect structure to isolate the semiconductor die with respect to inter-device interference. The shielding layer conforms to a geometry of the encapsulant and electrically connects to the ground pad. The shielding layer can be electrically connected to ground through a conductive pillar. A backside interconnect structure is formed over the interconnect structure, opposite the semiconductor die.

Abstract translation: 通过在衬底上形成互连结构来制造半导体器件。 将半导体管芯安装到互连结构。 半导体管芯与互连结构电连接。 在互连结构上形成接地焊盘。 在半导体管芯和互连结构上形成密封剂。 在形成密封剂之前，可以在半导体管芯上方形成屏蔽笼。 在形成互连结构之后，在密封剂之上形成屏蔽层，以便相对于器件间干扰来隔离半导体管芯。 屏蔽层符合密封剂的几何形状并且电连接到接地垫。 屏蔽层可以通过导电柱电连接到地面。 在互连结构上形成背面互连结构，与半导体管芯相对。

公开(公告)号：US20130175696A1

公开(公告)日：2013-07-11

申请号：US13782618

申请日：2013-03-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Hin Hwa Goh ,  Yu Gu ,  Il Kwon Shim ,  Rui Huang ,  Seng Guan Chow ,  Jianmin Fang ,  Xia Feng

IPC: H01L21/768 ,  H01L23/528

CPC classification number: H01L23/3114 ,  H01L21/31 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10156 ,  H01L2924/10157 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/19 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/214

Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Abstract translation: 半导体器件具有形成在半导体管芯的表面上的半导体管芯和导电层。 可以在半导体管芯中形成第一通道。 密封剂沉积在半导体管芯上。 可以在密封剂中形成第二通道。 在半导体管芯和第一导电层上形成第一绝缘层并进入第一沟道。 第一绝缘层延伸到第二通道中。 第一绝缘层的拉伸强度大于150MPa，伸长率在35-150％之间，厚度为2-30微米。 在形成第一绝缘层之前，可以在半导体管芯上方形成第二绝缘层。 在半导体管芯和密封剂上形成互连结构。 互连结构电连接到第一导电层。 第一绝缘层在形成互连结构期间提供应力释放。

公开(公告)号：US20130140719A1

公开(公告)日：2013-06-06

申请号：US13728012

申请日：2012-12-27

Applicant: Stats ChipPac, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu ,  Wei Meng ,  Chee Siang Ong

IPC: H01L23/29

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die and encapsulant deposited over the semiconductor die. A first insulating layer is formed over the die and encapsulant. The first insulating layer is cured with multiple dwell cycles to enhance adhesion to the die and encapsulant. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and first conductive layer. The second insulating layer is cured with multiple dwell cycles to enhance adhesion to the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. The first, second, and third insulating layers have different CTE. The second insulating layer or third insulating layer is cured to a dense state to block moisture.

Abstract translation: 半导体器件具有沉积在半导体管芯上的半导体管芯和密封剂。 在管芯和密封剂上形成第一绝缘层。 第一绝缘层通过多个停留周期固化，以增强与管芯和密封剂的粘合性。 在第一绝缘层上方形成第一导电层。 在第一绝缘层和第一导电层上形成第二绝缘层。 第二绝缘层通过多个停留循环固化，以增强对第一绝缘层和第一导电层的粘合性。 在第二绝缘层和第一导电层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 第一，第二和第三绝缘层具有不同的CTE。 第二绝缘层或第三绝缘层固化至致密状态以阻止水分。

公开(公告)号：US20130015555A1

公开(公告)日：2013-01-17

申请号：US13622280

申请日：2012-09-18

Applicant: STATS chipPAC, lTD.

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L29/02

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract translation: 半导体器件具有在其表面上形成有电感器的基板。 第一和第二接触垫形成在基板上。 在衬底和第一和第二接触焊盘之上形成钝化层。 在钝化层上形成保护层。 保护层在第一接触垫上移除，但不从第二接触垫移除。 导电层形成在第一接触焊盘上。 导电层被卷绕在基板的表面上以产生电感性质。 导电层的形成涉及使用湿蚀刻剂。 第二接触垫被保护层从湿蚀刻剂保护。 在第一接触垫上形成导电层之后，从第二接触焊盘去除保护层。 在第二接触垫上形成外部连接。

公开(公告)号：US09847324B2

公开(公告)日：2017-12-19

申请号：US14730030

申请日：2015-06-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L25/065 ,  H01L25/10 ,  H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/04 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2224/03002 ,  H01L2224/03003 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/0613 ,  H01L2224/12105 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14104 ,  H01L2224/16111 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/82005 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/82 ,  H01L2224/11 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/13015 ,  H01L2224/81

Abstract: A semiconductor device has a temporary carrier. A semiconductor die is oriented with an active surface toward, and mounted to, the temporary carrier. An encapsulant is deposited with a first surface over the temporary carrier and a second surface, opposite the first surface, is deposited over a backside of the semiconductor die. The temporary carrier is removed. A portion of the encapsulant in a periphery of the semiconductor die is removed to form an opening in the first surface of the encapsulant. An interconnect structure is formed over the active surface of the semiconductor die and extends into the opening in the encapsulant layer. A via is formed and extends from the second surface of the encapsulant to the opening. A first bump is formed in the via and electrically connects to the interconnect structure.