公开(公告)号：US20180159514A1

公开(公告)日：2018-06-07

申请号：US15829693

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Qi Lin

IPC: H03K3/013 ,  H04L25/49 ,  G11C7/02 ,  H04L25/06 ,  H03K5/153 ,  H04L25/03

CPC classification number: H03K3/013 ,  G11C7/02 ,  H03K5/153 ,  H04L25/03057 ,  H04L25/066 ,  H04L25/4902 ,  H04L25/4917

Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

公开(公告)号：US20180122444A1

公开(公告)日：2018-05-03

申请号：US15798136

申请日：2017-10-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/42 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20180083642A1

公开(公告)日：2018-03-22

申请号：US15667184

申请日：2017-08-02

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Hsuan-Jung Su ,  John Cronan Eble, III ,  Barry William Daly ,  Lei Luo ,  Teva J. Stone ,  John Wilson ,  Jihong Ren ,  Wayne D. Dettloff

IPC: H03L7/091 ,  H03L7/08 ,  H03L7/099

CPC classification number: H03L7/091 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  H03K5/1565 ,  H03L7/00 ,  H03L7/0802 ,  H03L7/099 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033

Abstract: A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

公开(公告)号：US09774441B2

公开(公告)日：2017-09-26

申请号：US15150355

申请日：2016-05-09

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Thomas H. Greer, III ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Mark A. Horowitz

IPC: H04L7/00 ,  H03L7/07 ,  H03L7/093 ,  H04L7/033 ,  H03L7/08 ,  H03L7/081 ,  H03L7/091

CPC classification number: H04L7/0012 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/0337

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.

公开(公告)号：US09742602B2

公开(公告)日：2017-08-22

申请号：US13896224

申请日：2013-05-16

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fred F. Chen ,  Andrew Ho ,  Ramin Farjad-Rad ,  John W. Poulton ,  Kevin S. Donnelly ,  Brian S. Leibowitz

IPC: H04L27/01 ,  H04L1/00 ,  H04L7/033 ,  H04L25/03 ,  H04L25/497 ,  H04W52/20 ,  H04L7/00 ,  H04L25/02 ,  H04W52/22

CPC classification number: H04L27/01 ,  H04L1/0026 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/497 ,  H04L2025/03503 ,  H04W52/20 ,  H04W52/225 ,  Y02D70/00

Abstract: A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

公开(公告)号：US09734879B2

公开(公告)日：2017-08-15

申请号：US14813028

申请日：2015-07-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C8/12 ,  G11C5/02 ,  G11C8/18 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US09564912B2

公开(公告)日：2017-02-07

申请号：US14990443

申请日：2016-01-07

Applicant: Rambus Inc.

Inventor： Marko Aleksić ,  Brian S. Leibowitz

IPC: G11C11/00 ,  H03L7/099 ,  H03L7/24

CPC classification number: H03L7/24 ,  H03K5/26 ,  H03K2005/00286 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

Abstract translation: 描述了具有注入锁定振荡器（ILO）的方法和装置。 在一些实施例中，国际劳工组织可以具有多个注入点和能够基于控制信号进行调整的自由运行频率。 在一些实施例中，ILO的每个注入点可以对应于相位调谐范围。 在一些实施例中，电路可以包括用于检测两个相邻相位调谐范围之间的相位边界的电路。 在一些实施例中，电路可以使用所检测的相位边界在两个相邻相位调谐范围之间切换。

公开(公告)号：US20160330013A1

公开(公告)日：2016-11-10

申请号：US15150355

申请日：2016-05-09

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Thomas H. Greer, III ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Mark A. Horowitz

IPC: H04L7/00 ,  H03L7/091 ,  H03L7/081 ,  H04L7/033 ,  H03L7/08

CPC classification number: H04L7/0012 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/091 ,  H03L7/093 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/0337

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.

Abstract translation: 一种用于执行时钟和数据恢复的系统和方法。 该系统根据到达信号和恢复的时钟信号之间的频率偏移或频率偏移的变化率的至少三个估计值来设置恢复的时钟信号的相位。

公开(公告)号：US20160226496A1

公开(公告)日：2016-08-04

申请号：US15009485

申请日：2016-01-28

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Brian S. Leibowitz

IPC: H03L1/00 ,  H03L7/24

CPC classification number: H03L1/00 ,  H03K3/0315 ,  H03L7/083 ,  H03L7/24

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

公开(公告)号：US09344074B2

公开(公告)日：2016-05-17

申请号：US14565802

申请日：2014-12-10

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Masum Hossain

IPC: H03K5/13 ,  H03L7/06 ,  H03L7/099 ,  H03K5/00 ,  H03L7/16

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.