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187 条记录 (耗时 0.029 秒)

    Fabricating interconnects and tips using sacrificial substrates
    151.
    发明授权
    Fabricating interconnects and tips using sacrificial substrates 失效
    使用牺牲衬底制造互连和尖端

    公开(公告)号：US5994152A

    公开(公告)日：1999-11-30

    申请号：US788740

    申请日：1997-01-24

    申请人： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu

    发明人： Igor Y. Khandros ,  Benjamin N. Eldridge ,  Gaetan L. Mathieu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/44

    摘要： Interconnection elements and/or tip structures for interconnection elements may first be fabricated upon sacrificial substrates for subsequent mounting to electronic components. In this manner, the electronic components are not `at risk` during the fabrication process. The sacrificial substrate establishes a predetermined spatial relationship between the interconnection elements which may be composite interconnection elements having a relatively soft elongate element as a core and a relatively hard (springy material) overcoat. Tip structures fabricated on sacrificial substrates may be provided with a surface texture optimized for mounting to any interconnection elements for making pressure connections to terminals of electronic components. Interconnection elements may be fabricated upon such tip structures, or may first be mounted to the electronic component and the tip structures joined to the free-ends of the interconnection elements. Tip structures formed as cantilever beams are described.

    摘要翻译： 用于互连元件的互连元件和/或尖端结构可以首先在牺牲基板上制造以用于随后安装到电子部件。 以这种方式，电子部件在制造过程中不“处于危险中”。 牺牲衬底在互连元件之间建立预定的空间关系，其可以是具有作为芯的相对柔软的细长元件和相对硬（弹性材料）外涂层的复合互连元件。 在牺牲基板上制造的尖端结构可以设置有优化的表面纹理，用于安装到任何互连元件，用于与电子部件的端子进行压力连接。 互连元件可以制造在这样的尖端结构上，或者可以首先安装到电子部件，并且尖端结构连接到互连元件的自由端。 描述形成为悬臂梁的尖端结构。

    Low noise integrated circuit and leadframe
    153.
    发明授权
    Low noise integrated circuit and leadframe 失效
    低噪声集成电路和引线框架

    公开(公告)号：US5065224A

    公开(公告)日：1991-11-12

    申请号：US243195

    申请日：1988-09-08

    申请人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

    发明人： Dana Fraser ,  Ray A. Mentzer ,  Jerry Gray ,  Geoff Hannington ,  Susan M. Keown ,  Gaetan L. Mathieu

    IPC分类号： H01L23/495 ,  H01L23/50 ,  H01L23/64 ,  H03K19/003 ,  H03K19/018

    CPC分类号： H01L23/645 ,  H01L23/49541 ,  H01L23/50 ,  H03K19/00353 ,  H03K19/01806 ,  H01L2924/0002 ,  H01L2924/30107 ,  H01L2924/3011

    摘要： To reduce the effect of on-chip power rail perturbation on integrated circuit performance, a lead configuration is provided having two or more leads originating at a single terminal, e.g. a pin. While merged near the pin in a common segment, the leads connect on the integrated circuit chip to respective isolated internal rails of the same type serving respective device stages. Preferably, the inductance of the common segment is minimized. In accordance with the invention, an octal registered transceiver is provided with isolated V.sub.cc and ground rails for the latch and output buffers. The lead configuration described above is used for both V.sub.cc and ground. Several circuits are improved to optimize performance of the device, including a DC Miller killer circuit. Also in accordance with the invention, the paddle of a PDIP leadframe is supported by tiebars that extends to the dambars at the sides of the leadframe. An additional lead is obtained from a conductive element originating near the paddle and supported by one of the two lead frame rails.

    摘要翻译： 为了减少片上电源轨扰动对集成电路性能的影响，提供了一种引线配置，其具有源自单个端子的两个或更多个引线，例如， 一个针。 当引脚在公共部分附近合并时，引线将集成电路芯片连接到相同类型的相互隔离的内部导轨，用于各个器件级。 优选地，公共片段的电感最小化。 根据本发明，八进制寄存收发器具有用于锁存和输出缓冲器的隔离Vcc和接地线。 上述引线结构用于Vcc和地线两者。 改进了几个电路以优化器件的性能，包括DC Miller杀手电路。 同样根据本发明，PDIP引线框的桨由在延伸到引线框架侧面的堤坝的拉杆支撑。 从源于接近桨叶并由两个引线框架轨道中的一个支撑的导电元件获得另外的引线。