公开(公告)号：US4082394A

公开(公告)日：1978-04-04

申请号：US756227

申请日：1977-01-03

Applicant: Ronald Walker Gedney ,  Robert Richard Rodite

Inventor： Ronald Walker Gedney ,  Robert Richard Rodite

IPC: H01L23/32 ,  H01L23/50 ,  H01L23/52 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H05K3/36 ,  H05K1/12

CPC classification number: H01R12/58 ,  H05K1/141 ,  H01L2224/16225 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2201/097 ,  H05K2201/09709 ,  H05K2201/10303 ,  H05K2201/10659 ,  H05K2201/10704 ,  H05K2201/10939 ,  H05K3/3447 ,  H05K3/368

Abstract: A package assembly which combines metallized ceramic technology and printed circuit board multilayer technology. A plurality of modules on a metallized ceramic substrate have closely spaced pins, for example, on 50 mil centers or grid, are plugged into a complex high precision multilayer printed circuit carrier. The pins are staggered in height with the longer pins having a relatively wide spacing, for example, on 100 mil centers or grid. The longer pins protrude through the high precision carrier and plug into a normal relatively simple and low cost printed circuit card or planar package.

公开(公告)号：US3665256A

公开(公告)日：1972-05-23

申请号：US3665256D

申请日：1968-10-15

Applicant: RCA CORP

Inventor： GOUN NATHAN M ,  WHEATELY CARL F JR

IPC: H01L21/56 ,  H01L23/495 ,  H05K1/02 ,  H01L1/12

CPC classification number: H05K1/0203 ,  H01L21/565 ,  H01L23/49568 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H05K2201/10659 ,  H05K2201/10689 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit chip having circuit elements capable of relatively high power operation is encapsulated in a body of polymeric material having the form of an elongated rectangular prism. Conductors are electrically coupled to the elements in the integrated circuit chip and extend outwardly of the body of polymeric material through its relatively long sides. Heat conductors thermally coupled to the integrated circuit chip extend outwardly of the package through the same sides as the electrical conductors and are adapted to couple the integrated circuit chip to an external heat dispersing means.

公开(公告)号：US09326380B2

公开(公告)日：2016-04-26

申请号：US13727701

申请日：2012-12-27

Applicant: INTEL CORPORATION

Inventor： Kuan-Yu Chen ,  Howard L. Heck

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H01R12/57 ,  H05K1/02 ,  H01R12/58

CPC classification number: H05K1/11 ,  H01R12/57 ,  H01R12/58 ,  H05K1/025 ,  H05K1/0269 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/115 ,  H05K2201/094 ,  H05K2201/09409 ,  H05K2201/10189 ,  H05K2201/10659 ,  H05K2201/2045 ,  H05K2203/163 ,  Y10T29/49124

Abstract: A universal serial bus hybrid footprint design is described herein. The design includes an outer row of one or more surface mount technology (SMT) contacts and an inner row of one or more printed through holes (PTH). The hybrid footprint design enables a data through put of at least 10 Gbps.

Abstract translation: 本文描述了通用串行总线混合覆盖设计。 该设计包括一排或多个表面贴装技术（SMT）触点和一列或多个印刷通孔（PTH）的内排。 混合足迹设计能够通过至少10 Gbps的数据进行数据传输。

公开(公告)号：US20150271922A1

公开(公告)日：2015-09-24

申请号：US14428008

申请日：2012-11-13

Applicant: Ryohei Kawabata ,  Yuichiro Takarabe

Inventor： Ryohei Kawabata ,  Yuichiro Takarabe

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/18 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/3447 ,  H05K2201/09063 ,  H05K2201/10166 ,  H05K2201/10409 ,  H05K2201/10659 ,  H05K2201/10757 ,  H05K2201/10969

Abstract: A printed circuit board mounted with a power module having both a plurality of lead terminals for soldering and at least one screw terminal for screwing includes a through hole which receives the lead terminal and is soldered to the lead terminal, and an electrode section provided with a screw hole fastened to the screw terminal via a screw. A groove is formed between the electrode section and the through hole so as to intersect with two common tangents each connecting, to an outer periphery of a land of the through hole, an outer periphery of a contact area of the electrode section which is in contact with a head bearing surface of a screw or a washer.

Abstract translation: 安装有具有用于焊接的多个引线端子和用于螺纹连接的至少一个螺钉端子的功率模块的印刷电路板包括：接纳引线端子并被焊接到引线端子的通孔;以及电极部， 螺丝孔通过螺钉固定在螺丝端子上。 在电极部分和通孔之间形成一个沟槽，以便与两个共同的切线相交，所述两个共同的切线连接到通孔的焊盘的外围，与接触的电极部分的接触区域的外周 具有螺钉或垫圈的头部轴承表面。

公开(公告)号：US09131615B2

公开(公告)日：2015-09-08

申请号：US14059777

申请日：2013-10-22

Applicant: CANON KABUSHIKI KAISHA

Inventor： Hideaki Hirasawa

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/34

CPC classification number: H05K1/11 ,  H05K1/0203 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10522 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract translation: 印刷电路板具有第一焊盘焊盘，第二焊盘焊盘和信号线图案。 第一焊盘被配置为与电子部件焊接。 第二焊盘被构造为蓄积焊料，第二焊盘位于沿着印刷电路的携带方向设置在第一焊盘的下游侧。 信号线图案包括未被抗蚀剂覆盖的暴露部分，暴露部分设置在焊接区域和防止桥接防止焊盘之间。

公开(公告)号：US08681509B2

公开(公告)日：2014-03-25

申请号：US12544156

申请日：2009-08-19

Applicant: Hideaki Hirasawa

Inventor： Hideaki Hirasawa

IPC: H05K7/10

CPC classification number: H05K1/11 ,  H05K1/0203 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10522 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract translation: 印刷电路板具有第一焊盘焊盘，第二焊盘焊盘和信号线图案。 第一焊盘被配置为与电子部件焊接。 第二焊盘被构造为蓄积焊料，第二焊盘位于沿着印刷电路的携带方向设置在第一焊盘的下游侧。 信号线图案包括未被抗蚀剂覆盖的暴露部分，暴露部分设置在焊接区域和防止桥接防止焊盘之间。

公开(公告)号：US20140041920A1

公开(公告)日：2014-02-13

申请号：US14059777

申请日：2013-10-22

Applicant: Canon Kabushiki Kaisha

Inventor： Hideaki Hirasawa

IPC: H05K1/11

CPC classification number: H05K1/11 ,  H05K1/0203 ,  H05K1/111 ,  H05K3/3421 ,  H05K3/3452 ,  H05K3/3468 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/10522 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2203/046 ,  Y02P70/611

Abstract: A printed circuit board has a first solder land, a second solder land, and a signal line pattern. The first solder land is configured to be soldered with an electronic part. The second solder land is configured to accumulate solder, the second solder land being disposed on a downstream side of the first solder land as viewed in a direction in which the printed circuit is carried. The signal line pattern includes an exposed part that is not covered with a resist, the exposed part being disposed between the solder land and the solder bridge prevention land.

Abstract translation: 印刷电路板具有第一焊盘焊盘，第二焊盘焊盘和信号线图案。 第一焊盘被配置为与电子部件焊接。 第二焊盘被构造为蓄积焊料，第二焊盘位于沿着印刷电路的携带方向设置在第一焊盘的下游侧。 信号线图案包括未被抗蚀剂覆盖的暴露部分，暴露部分设置在焊接区域和防止桥接防止焊盘之间。

公开(公告)号：US20110156203A1

公开(公告)日：2011-06-30

申请号：US12823678

申请日：2010-06-25

Applicant: Sang Wook PARK ,  Chul Hwan YOON ,  Youn Suk KIM ,  Seong Geun KIM ,  Sang Hee KIM ,  Jae Hyouck CHOI ,  Jun Kyung NA

Inventor： Sang Wook PARK ,  Chul Hwan YOON ,  Youn Suk KIM ,  Seong Geun KIM ,  Sang Hee KIM ,  Jae Hyouck CHOI ,  Jun Kyung NA

IPC: H01L29/86

CPC classification number: H05K3/328 ,  H01C1/014 ,  H01C1/14 ,  H01F17/0006 ,  H01F27/027 ,  H01G2/06 ,  H01G4/228 ,  H01L23/645 ,  H01L23/647 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/30107 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/10659 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There is provided an integrated passive device assembly. An integrated passive device assembly according to an aspect of the invention may include: a board having a wiring pattern provided thereon; an integrated passive device mounted on an upper surface of the board and having conductive patterns provided on upper and lower surfaces thereof; a first connection portion electrically connecting the conductive pattern, provided on the upper surface of the integrated passive device, and the wiring pattern to each other; and a second connection portion electrically connecting the conductive pattern, provided on the lower surface of the integrated passive device, and the wiring pattern to each other.

Abstract translation: 提供了集成的无源器件组件。 根据本发明的一个方面的集成无源器件组件可以包括：具有设置在其上的布线图案的板; 集成无源器件，其安装在所述板的上表面上并且具有设置在其上表面和下表面上的导电图案; 电连接所述集成无源器件的上表面上的导电图案和所述布线图案之间的第一连接部分; 以及将设置在集成无源器件的下表面上的导电图案与布线图案彼此电连接的第二连接部分。

公开(公告)号：US07652381B2

公开(公告)日：2010-01-26

申请号：US11055578

申请日：2005-02-09

Applicant: Kevin P. Grundy ,  Joseph C. Fjelstad ,  Gary Yasumura ,  William F. Wiedemann ,  Para K. Segaram

Inventor： Kevin P. Grundy ,  Joseph C. Fjelstad ,  Gary Yasumura ,  William F. Wiedemann ,  Para K. Segaram

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/13 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/16235 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/85399 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/308 ,  H05K3/3405 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/4046 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/0919 ,  H05K2201/092 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/1053 ,  H05K2201/10545 ,  H05K2201/1059 ,  H05K2201/10659 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10727 ,  H05K2201/10734 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Structures employed by a plurality of packages, printed circuit boards, connectors and interposers to create signal paths which reduce the deleterious signal quality issues associated with the use of through-holes. Disclosed structures can coexist with through-hole implementations.

Abstract translation: 由多个封装，印刷电路板，连接器和插入件采用的结构，以产生减少与使用通孔相关联的有害信号质量问题的信号路径。 公开的结构可以与通孔实现共存。

公开(公告)号：US20090149041A1

公开(公告)日：2009-06-11

申请号：US12349344

申请日：2009-01-06

Applicant: Danny L.C. Morlion ,  Steven E. Minich ,  Stephen B. Smith

Inventor： Danny L.C. Morlion ,  Steven E. Minich ,  Stephen B. Smith

IPC: H01R12/00

CPC classification number: H01R12/737 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0219 ,  H05K1/0237 ,  H05K1/114 ,  H05K1/115 ,  H05K1/14 ,  H05K3/308 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/1059 ,  H05K2201/10659

Abstract: An orthogonal backplane connector systems having midplane footprints that provide for continuity of impedance and signal integrity through the midplane and allow for the same connector to be coupled to either side of the midplane. This design creates an orthogonal interconnect without taking up unnecessary PCB real estate. The midplane circuit board may include a first differential signal pair of electrically conductive vias disposed in a first direction, and a second differential signal pair of electrically conductive vias disposed in a second direction that is generally orthogonal to the first direction. The first and second differential signal pair of electrically conductive vias are electrically connected through the midplane circuit board. Each pair may be associated with and be located in between ground vias. A ground via that is large relative to the signal vias may be provided. The second signal vias may comprise a shared signal via, receiving a contact from respective connectors connected to each side of the midplane circuit board. The second signal vias may comprise partial signal vias, extending from one or more sides partially into the midplane circuit board. The signal pairs may be offset from a via array centerline formed by the ground vias to correspond with mating ends of signal contacts of an electrical connector that likewise jog away from a centerline of a respective contact column of the connector.

Abstract translation: 正交背板连接器系统具有中间面积，其通过中平面提供阻抗和信号完整性的连续性，并允许相同的连接器耦合到中平面的任一侧。 该设计创建了一个正交互连，而不占用不必要的PCB空间。 中间平面电路板可以包括沿第一方向设置的导电通孔的第一差分信号对和沿大致正交于第一方向的第二方向设置的第二导电通孔对。 导电通孔的第一和第二差分信号对通过中平面电路板电连接。 每对可以与地面通孔相关联并位于其间。 可以提供相对于信号通路较大的接地通孔。 第二信号通孔可以包括共享信号通孔，从连接到中平面电路板的每一侧的相应连接器接收触点。 第二信号通孔可以包括从一个或多个侧面部分地延伸到中平面电路板中的部分信号通路。 信号对可以从由接地通孔形成的通孔阵列中心线偏移，以对应于同样从连接器的相应接触柱的中心线移开的电连接器的信号触头的配合端。