公开(公告)号：US09559644B2

公开(公告)日：2017-01-31

申请号：US14931448

申请日：2015-11-03

Applicant: RF Micro Devices, Inc.

Inventor： George Maxim ,  Dirk Robert Walter Leipold ,  Baker Scott ,  Ralph Christopher Nieri

IPC: H03F3/04 ,  H03F3/193 ,  H03F1/26 ,  H04B1/10 ,  H04B7/08 ,  H04W72/04 ,  H03F1/02 ,  H03F1/22

CPC classification number: H03F3/193 ,  H03F1/0261 ,  H03F1/223 ,  H03F1/26 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H04B1/1036 ,  H04B7/08 ,  H04B2001/1063 ,  H04W72/04

Abstract: Circuitry includes a floating-body main field-effect transistor (FET) device, a body-contacted cascode FET device, and biasing circuitry coupled to the floating-body main FET device and the body-contacted cascode FET device. The floating-body main FET device includes a gate contact, a drain contact, and a source contact. The body-contacted cascode FET device includes a gate contact, a drain contact coupled to a supply voltage, and a source contact coupled to the drain contact of the floating-body main FET device and to a body region of the body-contacted cascode FET device. The biasing circuitry is coupled to the gate contact of the floating-body main FET device and the gate contact of the body-contacted cascode FET device and configured to provide biasing signals to the floating-body main FET device and the body-contacted cascode FET device such that a majority of the supply voltage is provided across the body-contacted cascode FET device.

Abstract translation: 电路包括浮体主场效应晶体管（FET）器件，体接触共源共栅FET器件和耦合到浮体主FET器件和体接触共源共栅FET器件的偏置电路。 浮体主FET器件包括栅极接触，漏极接触和源极接触。 身体接触的共源共栅型FET器件包括栅极接触，耦合到电源电压的漏极接触以及耦合到浮体主FET器件的漏极接触和与身体接触的共源共栅FET的体区的源极接触 设备。 偏置电路耦合到浮体主FET器件的栅极接触和体接触共源共栅FET器件的栅极接触，并且被配置为向浮体主FET器件和体接触的共源共栅FET提供偏置信号 器件，使得大部分电源电压被提供在身体接触的共源共栅型FET器件上。

公开(公告)号：US09548768B2

公开(公告)日：2017-01-17

申请号：US14955461

申请日：2015-12-01

Applicant: RF Micro Devices, Inc.

Inventor： Nadim Khlat

IPC: H04M1/00 ,  H04B1/00 ,  H04B1/40 ,  H04W88/06

CPC classification number: H04B1/0064 ,  H04B1/0057 ,  H04B1/40 ,  H04W88/06

Abstract: Radio frequency (RF) front end circuitry includes first RF multiplexer circuitry and second RF multiplexer circuitry. The first RF multiplexer circuitry is a quadplexer, while the second RF multiplexer is a triplexer. The RF front end circuitry is configured to support the transmission and reception of signals within a first operating band, a second operating band, and a third operating band. Further, the RF front end circuitry is configured to support carrier aggregation configurations between the first operating band and the third operating band and the second operating band and the third operating band.

Abstract translation: 射频（RF）前端电路包括第一RF多路复用器电路和第二RF多路复用器电路。 第一RF多路复用器电路是四路复用器，而第二RF复用器是三工器。 RF前端电路被配置为支持第一工作频带，第二工作频带和第三操作频带内的信号的发送和接收。 此外，RF前端电路被配置为支持第一操作频带和第三操作频带以及第二操作频带和第三操作频带之间的载波聚合配置。

公开(公告)号：US09548258B2

公开(公告)日：2017-01-17

申请号：US14529870

申请日：2014-10-31

Applicant: RF Micro Devices, Inc.

Inventor： Julio C. Costa ,  David M. Shuttleworth ,  Michael J. Antonell

IPC: H01L23/373 ,  H01L27/12 ,  H01L23/48

Abstract: A semiconductor device that does not produce nonlinearities attributed to a high resistivity silicon handle interfaced with a dielectric region of a buried oxide (BOX) layer is disclosed. The semiconductor device includes a semiconductor stack structure with a first surface and a second surface wherein the second surface is on an opposite side of the semiconductor stack structure from the first surface. At least one device terminal is included in the semiconductor stack structure and at least one electrical contact extends from the second surface and is electrically coupled to the at least one device terminal. The semiconductor stack is protected by a polymer disposed on the first surface of the semiconductor stack. The polymer has high thermal conductivity and high electrical resistivity.

公开(公告)号：US09530853B2

公开(公告)日：2016-12-27

申请号：US14627340

申请日：2015-02-20

Applicant: RF Micro Devices, Inc.

Inventor： Haldane S. Henry ,  Eunki Hong ,  Charles S. Whitman

IPC: H01L21/44 ,  H01L29/47 ,  H01L29/812 ,  H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/475 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/66863 ,  H01L29/812

Abstract: A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 μA/mm and around 50 μA/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au).

Abstract translation: 公开了一种具有减小的漏电流的半导体器件及其制造方法。 半导体器件包括在源极接触和栅极接触之间的介电层内具有器件层，电介质层和栅极金属开口的衬底。 第一金属层设置在栅极金属开口内，并且第二金属层直接设置在第二金属层上，其中第二金属层被氧化并且具有在约4埃至约20埃的范围内以限制 总门外围的漏电流在约0.1μA/ mm到约50μA/ mm之间。 载流层设置在第二金属层上。 在一个实施例中，第一金属层是镍（Ni），第二金属层是钯（Pd），载流层是金（Au）。

公开(公告)号：US09530709B2

公开(公告)日：2016-12-27

申请号：US14885243

申请日：2015-10-16

Applicant: RF Micro Devices, Inc.

Inventor： Dirk Robert Walter Leipold ,  George Maxim ,  Julio C. Costa ,  Baker Scott

IPC: H01L23/31 ,  H01L21/306 ,  H01L21/304 ,  H01L21/02 ,  H01L21/683 ,  H01L23/29 ,  H01L23/373 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01Q1/50

CPC classification number: H01L23/315 ,  H01L21/02266 ,  H01L21/02282 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/20 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3731 ,  H01L23/3737 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L23/562 ,  H01L24/17 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/0002 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01Q1/50 ,  H05K1/0203 ,  H05K1/181 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.

Abstract translation: 公开了一种具有代替低电阻手柄层的保护层的印刷电路模块及其制造方法。 印刷电路模块包括具有附接到印刷电路基板的薄化管芯的印刷电路基板。 薄化的管芯包括印刷电路衬底上的至少一个器件层和至少一个器件层内的至少一个深阱。 保护层设置在至少一个深孔的上方，其中保护层具有大于2瓦/米开尔文（W / mK）的热导率和大于103欧姆 - 厘米的电阻率。

公开(公告)号：US20160351509A1

公开(公告)日：2016-12-01

申请号：US15080001

申请日：2016-03-24

Applicant: RF Micro Devices, Inc.

Inventor： Thong Dang ,  Dan Carey ,  Ma Shirley Asoy

IPC: H01L23/552 ,  H01L21/78 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/48 ,  H01L21/683 ,  H01L21/56 ,  H01L21/3205 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/268

CPC classification number: H01L23/552 ,  H01L21/268 ,  H01L21/31058 ,  H01L21/4817 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/04105 ,  H01L2224/12105

Abstract: The present disclosure integrates electromagnetic shielding into a wafer level fan-out packaging process. First, a mold wafer having multiple modules is provided. Each module includes a die with an I/O port and is surrounded by an inter-module area. A redistribution structure that includes a shield connected element coupled to the I/O port of each module is formed over a bottom surface of the mold wafer. The shield connected element extends laterally from the I/O port into the inter-module area for each module. Next, the mold wafer is sub-diced at each inter-module area to create a cavity. A portion of the shield connected element is then exposed through the bottom of each cavity. A shielding structure is formed over a top surface of the mold wafer and exposed faces of each cavity. The shielding structure is in contact with the shield connected element.

Abstract translation: 本公开将电磁屏蔽集成到晶片级扇出封装工艺中。 首先，提供具有多个模块的模具晶片。 每个模块包括一个具有I / O端口的模块，并被模块间区域包围。 包括耦合到每个模块的I / O端口的屏蔽连接元件的再分配结构形成在模具晶片的底表面上。 屏蔽连接元件从I / O端口横向延伸到每个模块的模块间区域。 接下来，在每个模块间区域对模具晶片进行子切割以形成空腔。 屏蔽连接元件的一部分然后通过每个空腔的底部暴露。 在模具晶片的顶表面和每个腔的暴露表面上形成屏蔽结构。 屏蔽结构与屏蔽连接的元件接触。

公开(公告)号：US20160343604A1

公开(公告)日：2016-11-24

申请号：US15085185

申请日：2016-03-30

Applicant: RF Micro Devices, Inc.

Inventor： Julio C. Costa ,  Jan Edward Vandemeer

IPC: H01L21/687 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/0692 ,  H01L21/6835 ,  H01L21/76251 ,  H01L21/76256 ,  H01L29/0649 ,  H01L29/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68368

Abstract: The present disclosure relates to a substrate structure with a buried dielectric layer for post-processing silicon handle elimination. The substrate structure includes a silicon handle layer, a first silicon oxide layer over the silicon handle layer, a buried dielectric layer over the first silicon oxide layer, where the buried dielectric layer is not formed from silicon oxide, a second silicon oxide layer over the buried dielectric layer, and a silicon epitaxy layer over the second silicon oxide layer. The buried dielectric layer provides extremely selective etch stop characteristics with respect to etching chemistries for silicon and silicon oxide.

Abstract translation: 本公开内容涉及一种具有用于后处理硅手柄消除的掩埋介质层的衬底结构。 所述衬底结构包括硅手柄层，所述硅手柄层上的第一氧化硅层，所述第一氧化硅层上的掩埋介电层，其中所述掩埋介电层不由氧化硅形成，所述第二氧化硅层 掩埋介电层和在第二氧化硅层上的硅外延层。 相对于硅和氧化硅的蚀刻化学性质，埋入的介电层提供非常选择性的蚀刻停止特性。

公开(公告)号：US09502510B2

公开(公告)日：2016-11-22

申请号：US14744275

申请日：2015-06-19

Applicant: RF Micro Devices, Inc.

Inventor： Peter J. Zampardi ,  Brian G. Moser ,  Jing Zhang ,  Thomas James Rogers ,  Dheeraj Mohata

IPC: H01L29/66 ,  H01L29/205 ,  H01L29/737 ,  H01L29/08

CPC classification number: H01L29/205 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to heterojunction bipolar transistors for improved radio frequency (RF) performance. In this regard, a heterojunction bipolar transistor includes a base, an emitter, and a collector. The base is formed over the collector such that a base-collector junction is formed between the base and the collector. The base-collector junction is configured to become forward-biased at a first turn-on voltage. The emitter is formed over the base such that a base-emitter junction is formed between the base and the emitter. The base-emitter junction is configured to become forward-biased at a second turn-on voltage, as opposed to the first turn-on voltage. Notably, the second turn-on voltage is lower than the first turn-on voltage.

Abstract translation: 本公开涉及用于改善射频（RF）性能的异质结双极晶体管。 在这方面，异质结双极晶体管包括基极，发射极和集电极。 基极形成在集电体上方，使得在基极和集电极之间形成基极 - 集电极结。 基极 - 集电极结被配置为在第一导通电压下正向偏置。 发射极形成在基极上，使得在基极和发射极之间形成基极 - 发射极结。 与第一导通电压相反，基极 - 发射极结被配置为以第二导通电压正向偏置。 值得注意的是，第二导通电压低于第一导通电压。

公开(公告)号：US09466430B2

公开(公告)日：2016-10-11

申请号：US14071025

申请日：2013-11-04

Applicant: RF Micro Devices, Inc.

Inventor： Kushal Bhattacharjee

IPC: H01L41/09 ,  H03H9/125 ,  H03H9/15 ,  H01G5/18 ,  H03H9/02 ,  H03H9/46 ,  H03H9/24 ,  B81B3/00

CPC classification number: H01G5/18 ,  B81B3/0086 ,  B81B2201/018 ,  B81B2201/0271 ,  B81B2201/032 ,  H03H9/02275 ,  H03H9/02409 ,  H03H9/2405 ,  H03H9/2463 ,  H03H9/462 ,  H03H9/467 ,  H03H2009/241

Abstract: A micro-electrical-mechanical systems (MEMS) device includes a substrate, one or more anchors formed on a first surface of the substrate, and a piezoelectric layer suspended over the first surface of the substrate by the one or more anchors. A first electrode may be provided on a first surface of the piezoelectric layer facing the first surface of the substrate, such that the first electrode is in contact with a first bimorph layer of the piezoelectric layer. A second electrode may be provided on a second surface of the piezoelectric layer opposite the first surface, such that the second electrode is in contact with a second bimorph layer of the piezoelectric layer.

Abstract translation: 微电气机械系统（MEMS）装置包括衬底，形成在衬底的第一表面上的一个或多个锚固体和通过一个或多个锚固件悬挂在衬底的第一表面上的压电层。 第一电极可以设置在面向基板的第一表面的压电层的第一表面上，使得第一电极与压电层的第一双压电晶片层接触。 第二电极可以设置在与第一表面相对的压电层的第二表面上，使得第二电极与压电层的第二双晶片层接触。

公开(公告)号：US20160284570A1

公开(公告)日：2016-09-29

申请号：US15173037

申请日：2016-06-03

Applicant: RF Micro Devices, Inc.

Inventor： Thomas Scott Morris ,  David Jandzinski ,  Stephen Parker ,  Jon Chadwick ,  Julio C. Costa

IPC: H01L21/56 ,  H01L23/373 ,  H01L23/29

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L21/568 ,  H01L23/29 ,  H01L23/3135 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/10 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L21/56 ,  H01L2221/68304 ,  H01L21/304 ,  H01L21/30604 ,  H01L2221/68381

Abstract: The present disclosure relates to a semiconductor package having encapsulated dies with enhanced thermal performance. The semiconductor package includes a carrier, an etched flip chip die attached to a top surface of the carrier, a first mold compound, and a second mold compound. The etched flip chip die includes a device layer and essentially does not include a substrate. The first mold compound resides on the top surface of the carrier, surrounds the etched flip chip die, and extends beyond a top surface of the etched flip chip die to form a cavity, to which the top surface of the etched flip chip die is exposed. The second mold compound fills the cavity and is in contact with the top surface of the etched flip chip die. The second mold compound having a high thermal conductivity improves thermal performance of the etched flip chip die.

Abstract translation: 本公开涉及具有增强的热性能的具有密封模具的半导体封装。 半导体封装包括载体，附着在载体的顶表面上的蚀刻倒装芯片模具，第一模具化合物和第二模具化合物。 蚀刻的倒装芯片芯片包括器件层，并且基本上不包括衬底。 第一模具化合物位于载体的顶表面上，围绕蚀刻的倒装芯片模具，并且延伸超过蚀刻的倒装芯片模具的顶表面，以形成空腔，蚀刻的倒装芯片裸片的顶表面露出 。 第二模具化合物填充空腔并与蚀刻的倒装芯片模具的顶表面接触。 具有高导热性的第二模具化合物改善了蚀刻的倒装芯片的热性能。