公开(公告)号：US20070246853A1

公开(公告)日：2007-10-25

申请号：US11758752

申请日：2007-06-06

Applicant: S. CHEY ,  Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

Inventor： S. CHEY ,  Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

IPC: B29C70/88 ,  B29C33/38

CPC classification number: B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

Abstract: A system and method are provided for injection molding conductive bonding material into a plurality of cavities in a mold within a vacuum chamber. A mold and a fill head are located within a vacuum chamber, wherein the mold includes a plurality of cavities. A vacuum is created within the vacuum chamber, thereby removing air from the chamber and from the cavities. Optionally, rotational motion is provided to at least one of the mold and the fill head while the fill head is in substantial contact with the mold. Conductive bonding material is forced out of the fill head toward the mold, and into at least one of the cavities, while a vacuum is maintained in the vacuum chamber.

Abstract translation: 提供了一种系统和方法，用于将导电接合材料注射到真空室内的模具中的多个空腔中。 模具和填充头位于真空室内，其中模具包括多个空腔。 在真空室内产生真空，从而从腔室和空腔中除去空气。 可选地，当填充头与模具基本接触时，将旋转运动提供给模具和填充头中的至少一个。 当在真空室中保持真空时，导电接合材料被迫从灌装头朝向模具，并进入至少一个空腔中。

公开(公告)号：US20070246511A1

公开(公告)日：2007-10-25

申请号：US11409244

申请日：2006-04-21

Applicant: Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

Inventor： Steven Cordes ,  Peter Gruber ,  John Knickerbocker ,  James Speidell

IPC: A47J36/02

CPC classification number: H05K3/3484 ,  B23K3/0607 ,  B23K2101/42 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/09472 ,  H05K2203/0126 ,  H05K2203/043 ,  H05K2203/0568

Abstract: A system, method, and apparatus of providing conductive bonding material into a plurality of cavities in a circuit supporting substrate is disclosed. The method comprises placing a fill head in substantial contact with a circuit supporting substrate. The circuit supporting substrate includes at least one cavity. A linear motion or a rotational motion is provided to at least one of the circuit supporting substrate and the fill head while the fill head is in substantial contact with the circuit supporting substrate. Conductive bonding material is forced out of the fill head toward the circuit supporting substrate. The conductive bonding material is provided into the at least one cavity contemporaneous with the at least one cavity being in proximity to the fill head.

Abstract translation: 公开了一种在电路支撑衬底中的多个空腔中提供导电接合材料的系统，方法和装置。 该方法包括将填充头放置成与电路支撑衬底基本接触。 电路支撑衬底包括至少一个空腔。 当填充头与电路支撑衬底基本接触时，向电路支撑衬底和填充头中的至少一个提供直线运动或旋转运动。 导电接合材料被迫从填充头朝向电路支撑基板排出。 所述导电接合材料被提供到与所述至少一个空腔同时的至少一个空腔中，所述至少一个空腔在所述填充头附近。

公开(公告)号：US20060043608A1

公开(公告)日：2006-03-02

申请号：US10711185

申请日：2004-08-31

Applicant: William Bernier ,  Marie Cole ,  Mukta Farooq ,  John Knickerbocker ,  Tasha Lopez ,  Roger Quon ,  David Welsh

Inventor： William Bernier ,  Marie Cole ,  Mukta Farooq ,  John Knickerbocker ,  Tasha Lopez ,  Roger Quon ,  David Welsh

IPC: H01L23/48

CPC classification number: H05K3/321 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13339 ,  H01L2224/13464 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/838 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K2201/0212 ,  H05K2201/0248 ,  H05K2201/0373 ,  H05K2201/1025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: Disclosed is a laminated (or non-laminated) conductive interconnection for joining an integrated circuit device to a device carrier, where the conductive interconnection comprises alternating metal layers and polymer layers. In addition, the polymer can include dendrites, metal projections from the carrier or device, and/or micelle brushes on the outer portion of the polymer. The polymer layers include metal particles and the alternating metal layers and polymer layers form either a cube-shaped structure or a cylinder-shaped structure.

Abstract translation: 公开了用于将集成电路器件连接到器件载体的层压（或非层叠）导电互连，其中导电互连包括交替的金属层和聚合物层。 此外，聚合物可以包括枝晶，来自载体或器件的金属突起，和/或聚合物外部的胶束刷。 聚合物层包括金属颗粒，并且交替的金属层和聚合物层形成立方体结构或圆柱形结构。

公开(公告)号：US08388782B2

公开(公告)日：2013-03-05

申请号：US12788832

申请日：2010-05-27

Applicant: Paul S. Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prahbakar ,  Peter J. Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

Inventor： Paul S. Andry ,  Bing Dang ,  John Knickerbocker ,  Aparna Prahbakar ,  Peter J. Sorce ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC: B32B38/10 ,  B32B37/12

CPC classification number: H01L21/67132 ,  C09J5/06 ,  C09J2203/326 ,  C09J2479/08 ,  H01L21/6835 ,  H01L2221/6835 ,  H01L2221/68381 ,  Y10T156/1158

Abstract: A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.

Abstract translation: 一种用于将处理器附接到晶片的方法，所述晶片包括集成电路（IC），包括在所述晶片上形成粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。 一种用于将处理器附接到晶片的系统，包括IC的晶片包括位于晶片上的粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。

公开(公告)号：US20110290413A1

公开(公告)日：2011-12-01

申请号：US12788839

申请日：2010-05-27

Applicant: Bing Dang ,  Matthew Farinelli ,  John Knickerbocker ,  Aparna Prabhakar ,  Robert E. Trzcinski ,  Cornelia K. Tsang

Inventor： Bing Dang ,  Matthew Farinelli ,  John Knickerbocker ,  Aparna Prabhakar ,  Robert E. Trzcinski ,  Cornelia K. Tsang

IPC: B32B38/10 ,  B29C65/16

CPC classification number: H01L21/6835 ,  B23K26/0622 ,  B23K26/0823 ,  B23K26/361 ,  B23K26/57 ,  B23K2101/40 ,  B23K2103/42 ,  B23K2103/50 ,  C09J5/00 ,  C09J2203/326 ,  C09J2205/302 ,  C09J2400/22 ,  H01L2221/68381 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.

Abstract translation: 一种用于从晶片释放处理器的方法，所述晶片包括集成电路（IC），包括使用包含热固性聚合物的粘合剂将所述处理器附接到所述晶片，所述处理器包括在约193的波长范围内是透明的材料 纳米（nm）至约400nm; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。

公开(公告)号：US20080009101A1

公开(公告)日：2008-01-10

申请号：US11858147

申请日：2007-09-20

Applicant: William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

Inventor： William Bernier ,  Tien-Jen Cheng ,  Marie Cole ,  David Eichstadt ,  Mukta Farooq ,  John Fitzsimmons ,  Lewis Goldmann ,  John Knickerbocker ,  Tasha Lopez ,  David Welsh

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

Abstract translation: 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20070272389A1

公开(公告)日：2007-11-29

申请号：US11396107

申请日：2006-03-31

Applicant: Peter Gruber ,  John Knickerbocker

Inventor： Peter Gruber ,  John Knickerbocker

IPC: B22D11/124 ,  B05D5/12

CPC classification number: H05K3/3457 ,  H01L21/288 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/11009 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/1319 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2203/0113 ,  H05K2203/0557 ,  H01L2924/00

Abstract: A method and apparatus for the formation of coplanar electrical interconnectors. Solder material is deposited onto a wafer, substrate, or other component of an electrical package using a complaint mold such that the terminal ends of the solder material being deposited, i.e., the ends opposite to those forming an attachment to the wafer, substrate, or other component of an electrical package are coplanar with one another. A complaint mold is used having one or more conduits for receiving solder material and having a compliant side and a planar side. The compliant side of the mold is positioned adjacent to the wafer, substrate, or other component of an electrical package allowing solder material to be deposited onto the surface thereof such that the planar side of the compliant mold provides coplanar interconnectors. An Injection Molded Solder (IMS) head can be used as the means for filling the conduits of the compliant mold of the present invention.

Abstract translation: 用于形成共面电连接器的方法和装置。 使用投诉模具将焊料沉积到电气封装的晶片，基板或其他部件上，使得焊料材料的末端被沉积，即与形成与晶片，基板或附件形成连接的端部相对的端部 电气封装的其他部件彼此共面。 使用投诉模具具有一个或多个用于接收焊料材料并具有柔性侧面和平面侧的导管。 模具的柔性侧被定位成与电气封装的晶片，衬底或其它部件相邻，允许将焊料材料沉积到其表面上，使得柔性模具的平面侧提供共面的互连器件。 可以使用注射成型焊料（IMS）头作为填充本​​发明的柔性模具的导管的装置。

公开(公告)号：US20070222065A1

公开(公告)日：2007-09-27

申请号：US11385121

申请日：2006-03-21

Applicant: Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

Inventor： Paul Andry ,  Leena Buchwalter ,  Raymond Horton ,  John Knickerbocker ,  Cornelia Tsang ,  Steven Wright

IPC: H01L21/00 ,  H01L23/34

CPC classification number: H01L24/81 ,  H01L23/544 ,  H01L24/48 ,  H01L24/97 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48227 ,  H01L2224/81001 ,  H01L2224/81054 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/20109 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.

Abstract translation: 一种电子潜水及其制造方法。 所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准 集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

公开(公告)号：US20070099342A1

公开(公告)日：2007-05-03

申请号：US11566956

申请日：2006-12-05

Applicant: John Knickerbocker ,  Voya Markovich ,  Thomas Miller ,  William Rudik

Inventor： John Knickerbocker ,  Voya Markovich ,  Thomas Miller ,  William Rudik

IPC: H01L21/00

CPC classification number: H05K1/0271 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/384 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/1152 ,  H01L2924/00

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Abstract translation: 提供了具有降低的BGA焊盘与层压体表面的粘附性的球栅阵列封装及其制造方法。

公开(公告)号：US20050110160A1

公开(公告)日：2005-05-26

申请号：US10721984

申请日：2003-11-25

Applicant: Mukta Faroog ,  John Knickerbocker ,  Frank Pompeo ,  Subhash Shinde

Inventor： Mukta Faroog ,  John Knickerbocker ,  Frank Pompeo ,  Subhash Shinde

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/36 ,  H01L23/498 ,  H01L21/44 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/36 ,  H01L23/49827 ,  H01L24/75 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/16195

Abstract: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Abstract translation: 在本发明中，半导体芯片通过插入件结构与基板（例如有机，陶瓷等）电连接。 插入器结构包括弹性体柔性材料，其包括具有预定形状的通过连接的冶金。 在典型的实施例中，冶金通孔连接将半导体芯片的凸起下金属化电连接到衬底的顶表面金属化。 通过利用根据本发明的插入器结构，可以减轻与先前的半导体模块设计相关的问题。