公开(公告)号：US06888716B2

公开(公告)日：2005-05-03

申请号：US10767559

申请日：2004-01-28

Applicant: Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

Inventor： Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

IPC: H01L21/02 ,  H01L21/60 ,  H01L23/522 ,  H01L27/08 ,  H01G4/228

CPC classification number: H01L24/11 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract translation: 公开了一种制造片上去耦电容器的方法，其有助于防止在高浪涌电流条件下电网上的L di / dt电压下降。 在电网之间直接插入去耦电容器大大降低了电感L，并提供去耦以减少最高可能的频率噪声。 本发明具体描述了其中去耦电容器位于顶层金属化和具有多个开口或棒几何形状以提供电网和顶部去耦电容器电极接触的标准突起触头之间的工艺流程。

公开(公告)号：US06706584B2

公开(公告)日：2004-03-16

申请号：US09895362

申请日：2001-06-29

Applicant: Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

Inventor： Richard Scott List ,  Bruce A. Block ,  Mark T. Bohr

IPC: H01L218242

CPC classification number: H01L24/11 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/55 ,  H01L28/75 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/0508 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01038 ,  H01L2924/01044 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A method of fabricating an on-chip decoupling capacitor which helps prevent L di/dt voltage droop on the power grid for high surge current conditions is disclosed. Inclusion of the decoupling capacitor on die directly between the power grid greatly reduces the inductance L, and provides decoupling to reduce the highest possible frequency noise. This invention specifically describes the process flow in which the decoupling capacitor is located between the top layer metallization and the standard bump contacts which have either multiple openings or bar geometries to provide both power grid and top decoupling capacitor electrode contacts.

Abstract translation: 公开了一种制造片上去耦电容器的方法，其有助于防止在高浪涌电流条件下电网上的L di / dt电压下降。 在电网之间直接插入去耦电容器大大降低了电感L，并提供去耦以减少最高可能的频率噪声。 本发明具体描述了其中去耦电容器位于顶层金属化和具有多个开口或棒几何形状以提供电网和顶部去耦电容器电极接触的标准突起触头之间的工艺流程。

公开(公告)号：US06617681B1

公开(公告)日：2003-09-09

申请号：US09340530

申请日：1999-06-28

Applicant: Mark T. Bohr

Inventor： Mark T. Bohr

IPC: H01L23522

CPC classification number: H01L23/147 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49165

Abstract: A structure suitable for connecting an integrated circuit to a supporting substrate wherein the structure has thermal expansion characteristics well-matched to the integrated circuit is an interposer. The integrated circuit and the interposer are comprised of bodies that have substantially similar coefficients of thermal expansion. The interposer has a first surface adapted to electrically and mechanically couple to the integrated circuit. The interposer has a second surface adapted to electrically and mechanically couple to a supporting substrate. Electrically conductive vias provide signal pathways between the first surface and the second surface of the interposer. Various circuit elements may be incorporated into the interposer. These circuit elements may be active, passive, or a combination of active and passive elements.

公开(公告)号：US5976939A

公开(公告)日：1999-11-02

申请号：US498028

申请日：1995-07-03

Applicant: Scott Thompson ,  Mark T. Bohr ,  Paul A. Packan

Inventor： Scott Thompson ,  Mark T. Bohr ,  Paul A. Packan

IPC: H01L21/225 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/6659 ,  H01L21/2257 ,  H01L21/823814 ,  H01L29/6656

Abstract: A process for fabricating a source and drain region which includes a more lightly doped source and drain tip region immediately adjacent to the gate and a more heavily doped main portion of the source and drain region spaced apart from the gate. A first layer of glass (2% BSG) is used to provide the source of doping for the tip region and a second layer of glass (6% BSG) is used to provide the dopant for the more heavily doped major portion of source and drain regions. Spacers are formed between the glass layers to define the tip region from the main portion of the source and drain regions.

Abstract translation: 一种用于制造源极和漏极区的工艺，其包括与栅极紧邻的更轻掺杂的源极和漏极尖端区域以及与栅极间隔开的源极和漏极区域的更重掺杂的主要部分。 使用第一层玻璃（2％BSG）为尖端区域提供掺杂源，并且使用第二层玻璃（6％BSG）为源和漏极的更重掺杂的主要部分提供掺杂剂 地区。 间隔件形成在玻璃层之间，以限定源区和漏区的主要部分的尖端区域。

公开(公告)号：US5734187A

公开(公告)日：1998-03-31

申请号：US876473

申请日：1997-06-16

Applicant: Mark T. Bohr ,  Jeffrey K. Greason

Inventor： Mark T. Bohr ,  Jeffrey K. Greason

IPC: H01L27/11 ,  G01C11/34 ,  G11C5/00 ,  G11C11/34 ,  G11C11/40 ,  G11C14/00 ,  G11C15/04 ,  H01L21/8244 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

Abstract: A memory cell with vertically stacked crossovers. In prior memory cells, crossover connections within the memory cell were implemented in the same device layer. This wasted valuable design space, since the crossovers were therefore required to sit side-by-side in the layout design. The present invention implements crossovers in different materials on different device layers. The crossovers may therefore be vertically stacked on top of each other, reducing the area of the memory cell.

Abstract translation: 具有垂直堆叠交叉的存储单元。 在先前的存储器单元中，存储器单元内的交叉连接被实现在相同的器件层中。 这浪费了宝贵的设计空间，因为交叉路口因此需要在布局设计中并排。 本发明在不同的器件层上实现不同材料的交叉。 因此，交叉可以垂直堆叠在彼此的顶部，从而减小存储单元的面积。

公开(公告)号：US4536947A

公开(公告)日：1985-08-27

申请号：US627061

申请日：1984-07-02

Applicant: Mark T. Bohr ,  Ken K. Yu ,  Leo D. Yau ,  Shyam G. Garg

Inventor： Mark T. Bohr ,  Ken K. Yu ,  Leo D. Yau ,  Shyam G. Garg

IPC: H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/306 ,  H01L21/31

CPC classification number: H01L27/1085 ,  H01L21/8238 ,  H01L27/108 ,  Y10S148/014 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/106 ,  Y10S148/117 ,  Y10S438/911

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

Abstract translation: 描述了一种特别适用于形成动态存储单元的CMOS工艺。 电池形成在n阱中，并且由第一多晶硅层形成的单个板构件用于整个阵列。 当沉积第二层多晶硅时，第一多晶硅层的独特蚀刻防止发生桁条。 三层电介质用于阵列中的电容器。 使用磷掺杂玻璃公开了新的“后端”处理。

公开(公告)号：US4505026A

公开(公告)日：1985-03-19

申请号：US513658

申请日：1983-07-14

Applicant: Mark T. Bohr ,  Ken K. Yu ,  Leo D. Yau ,  Shyam G. Garg

Inventor： Mark T. Bohr ,  Ken K. Yu ,  Leo D. Yau ,  Shyam G. Garg

IPC: H01L27/10 ,  H01L21/033 ,  H01L21/306 ,  H01L21/334 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/78 ,  H01L21/31

CPC classification number: H01L27/1085 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/66181 ,  H01L27/108

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

Abstract translation: 描述了一种特别适用于形成动态存储单元的CMOS工艺。 电池形成在n阱中，并且由第一多晶硅层形成的单个板构件用于整个阵列。 当沉积第二层多晶硅时，第一多晶硅层的独特蚀刻防止发生桁条。 三层电介质用于阵列中的电容器。 使用磷掺杂玻璃公开了新的“后端”处理。

公开(公告)号：US10685947B2

公开(公告)日：2020-06-16

申请号：US15869637

申请日：2018-01-12

Applicant: Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. Mc Cullough

Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. Mc Cullough

IPC: H01L23/48 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US20170040218A1

公开(公告)日：2017-02-09

申请号：US15299106

申请日：2016-10-20

Applicant: Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/51

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract translation: 晶体管包括衬底，衬底上的一对间隔物，衬底上的栅介质层和一对间隔物之间​​，栅极电介质层上的栅电极层和一对衬垫之间的绝缘帽层 栅极电极层和一对间隔物之间​​，以及与该对间隔物相邻的一对扩散区域。 绝缘盖层形成了与栅极自对准的防蚀结构，并防止接触蚀刻暴露栅电极，从而防止栅极和接触之间的短路。 绝缘体盖层能够进行自对准触点，允许对图案化限制更坚固的较宽触点的初始图案化。

公开(公告)号：US09449913B2

公开(公告)日：2016-09-20

申请号：US13994668

申请日：2011-10-28

Applicant: Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

Inventor： Kevin J. Lee ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Christopher M. Pelto ,  Hiten Kothari ,  Seshu V. Sattiraju ,  Hang-Shing Ma

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/29 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76898 ,  H01L23/291 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/0105 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract translation: 描述了三维互连结构和制造方法，其中金属再分配层（RDL）与硅通孔（TSV）集成并且使用单个镶嵌型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。