公开(公告)号：US20150061143A1

公开(公告)日：2015-03-05

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L23/528 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US20140264946A1

公开(公告)日：2014-09-18

申请号：US13833921

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Marcus Bernard Hsu ,  David Fraser Rae

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract translation: 为了实现具有有利地降低的高度的封装封装，第一封装衬底具有尺寸适于接收第二封装管芯的窗口。 第一封装衬底通过多个封装到封装互连而互连到第二封装衬底，使得第一和第二衬底被间隙隔开。 第二封装管芯具有大于间隙的厚度，使得第二封装管芯至少部分地设置在第一封装衬底的窗口内。

公开(公告)号：US09806063B2

公开(公告)日：2017-10-31

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

公开(公告)号：US09609751B2

公开(公告)日：2017-03-28

申请号：US14251486

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H01L23/498

CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

公开(公告)号：US09601435B2

公开(公告)日：2017-03-21

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  David Fraser Rae ,  Rajneesh Kumar ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/16 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

公开(公告)号：US20160035622A1

公开(公告)日：2016-02-04

申请号：US14447399

申请日：2014-07-30

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Houssam Wafic Jomaa ,  David Fraser Rae ,  Layal Rouhana ,  Omar James Bchir

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L21/76852 ,  H01L21/4825 ,  H01L21/76879 ,  H01L23/4952 ,  H01L23/49527 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/53204 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/00014

Abstract: Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.

Abstract translation: 一些特征涉及集成器件，其包括第一衬底，耦合到第一衬底的第一阻焊层，耦合到第一阻焊层的第二阻焊层和第一和第二阻焊层中的开口， 开口，其包括完全被第二阻焊层覆盖的侧壁，其中第二阻焊层的侧壁覆盖第一阻焊层的侧壁。 在一些实施方案中，开口至少部分地填充有导电材料。 导电材料包括焊料和/或互连中的一种。 集成器件包括耦合到导电材料的第一互连。 第一互连是至少焊料和/或互连球之一。 在一些实施方案中，集成器件包括耦合到衬底的焊盘和耦合到焊盘的第一互连。

公开(公告)号：US20140227835A1

公开(公告)日：2014-08-14

申请号：US14255349

申请日：2014-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： Omar James Bchir ,  Milind Pravin Shah ,  Sashidhar Movva

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.

Abstract translation: 用于制造封装集成电路的背面模具配置（BSMC）工艺包括将模具化合物施加到与附接模具相对的封装基板的一侧。 将模具化合物沉积在电介质（例如光致抗蚀剂）上。 在将模具连接到包装基板上以暴露包装基板的接触垫之后，模制化合物和电介质被图案化。 在模制化合物和电介质图案化之后，封装连接通过模具化合物和电介质耦合到接触垫。 围绕包装连接的模具化合物减少处理期间包装基材的翘曲。 此外，在连接芯片之后对电介质进行图案化提高了封装连接的可靠性。

公开(公告)号：US20240371736A1

公开(公告)日：2024-11-07

申请号：US18310331

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Dongming He ,  Ryan Lane ,  Kuiwon Kang ,  Lily Zhao

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L25/16 ,  H01L25/18 ,  H10B80/00

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

公开(公告)号：US10199152B2

公开(公告)日：2019-02-05

申请号：US14743623

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Mete Erturk ,  Ravindra Vaman Shenoy ,  Kwan-yu Lai ,  Jitae Kim ,  Donald William Kidwell, Jr. ,  Jon Bradley Lasiter ,  James Thomas Doyle ,  Omar James Bchir

IPC: H01F5/00 ,  H01F27/28 ,  H01F1/147 ,  H01F27/24 ,  H01F41/02 ,  H01F41/14 ,  H05K1/11 ,  H05K1/18 ,  H01F17/00 ,  H01F41/04 ,  H05K1/16 ,  H01L23/64 ,  H01L23/00

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

公开(公告)号：US09679841B2

公开(公告)日：2017-06-13

申请号：US14276763

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Kuiwon Kang ,  Chin-Kwan Kim

IPC: H01L23/535 ,  H01L23/522 ,  H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.