公开(公告)号：US20170033033A1

公开(公告)日：2017-02-02

申请号：US15293584

申请日：2016-10-14

Applicant: RENESAS ELECTRONICS CORPORATION ,  RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.

Inventor： Hajime HASEBE ,  Tadatoshi DANNO ,  Yukihiro SATOU

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49 ,  H01L23/4952 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29339 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/484 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/85439 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/351 ,  Y10T29/49121 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract translation: 在非引线型半导体器件中，突片，突片悬挂引线和其它引线暴露于密封构件的一个表面。 半导体元件被定位在密封构件内并用粘合剂固定到突片的表面。 突片形成为比半导体元件大，使得突片的外周边缘位于半导体元件的外周边缘的外侧。 在位于半导体元件固定的区域与电线连接的电线连接区域之间的突片表面部分中形成有沟槽，该沟槽形成为围绕半导体元件固定区域，从而防止剥离 在半导体元件固定的突片与构成封装的树脂之间。

公开(公告)号：US20160133549A1

公开(公告)日：2016-05-12

申请号：US14981452

申请日：2015-12-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO ,  Hirokazu KATO

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

公开(公告)号：US20160049375A1

公开(公告)日：2016-02-18

申请号：US14925584

申请日：2015-10-28

Applicant: Renesas Electronics Corporation

Inventor： Ippei KUME ,  Takashi ONIZAWA ,  Takashi HASE ,  Shigeru HIRAO ,  Tadatoshi DANNO

IPC: H01L23/00 ,  H01L29/417 ,  H01L29/778 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/3178 ,  H01L29/1095 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7842 ,  H01L29/7849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a substrate which includes a first face. The device also includes a buffer layer, a semiconductor layer, source and drain electrodes, and a gate electrode. A trench is formed on the semiconductor layer so that the trench surrounds the source electrode, the drain electrode, and the gate electrode in a plan view, the trench passes through the semiconductor layer and the buffer layer, and a bottom of the trench reaches at least an inside of the substrate. A distance from the first face of the substrate to the bottom of the trench is 100 nm or more in a thickness direction of the substrate.

Abstract translation: 半导体器件包括包括第一面的衬底。 该器件还包括缓冲层，半导体层，源极和漏极以及栅电极。 在半导体层上形成沟槽，使得沟槽在平面图中围绕源电极，漏电极和栅电极，沟槽穿过半导体层和缓冲层，并且沟槽的底部到达 至少衬底的内部。 从衬底的第一面到沟槽的底部的距离在衬底的厚度方向上为100nm以上。

公开(公告)号：US20140299979A1

公开(公告)日：2014-10-09

申请号：US14048804

申请日：2013-10-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tadatoshi DANNO ,  Toshiyuki HATA ,  Yuichi MACHIDA

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49568 ,  H01L21/4875 ,  H01L23/3107 ,  H01L23/4006 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/97 ,  H01L2023/4056 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The reliability of a semiconductor device is improved. A semiconductor device has a first metal plate and a second metal plate electrically isolated from the first metal plate. Over the first metal plate, a first semiconductor chip including a transistor element formed thereover is mounted. Whereas, over the second metal plate, a second semiconductor chip including a diode element formed thereover is mounted. Further, the semiconductor device has a lead group including a plurality of leads electrically coupled with the first semiconductor chip or the second semiconductor chip. The first and second metal plates are arranged along the X direction in which the leads are arrayed. Herein, the area of the peripheral region of the first semiconductor chip in the first metal plate is set larger than the area of the peripheral region of the second semiconductor chip in the second metal plate.

Abstract translation: 提高了半导体器件的可靠性。 半导体器件具有与第一金属板电隔离的第一金属板和第二金属板。 在第一金属板上安装包括形成在其上的晶体管元件的第一半导体芯片。 而在第二金属板上安装包括形成在其上的二极管元件的第二半导体芯片。 此外，半导体器件具有包括与第一半导体芯片或第二半导体芯片电耦合的多个引线的引线组。 第一和第二金属板沿引线排列的X方向排列。 这里，将第一金属板中的第一半导体芯片的周边区域的面积设定为大于第二金属板中的第二半导体芯片的周边区域的面积。

公开(公告)号：US20190198477A1

公开(公告)日：2019-06-27

申请号：US16290804

申请日：2019-03-01

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Hiroyoshi TAYA ,  Yoshiharu SHIMIZU

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/78 ,  H01L21/67 ,  H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/544

CPC classification number: H01L24/83 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/67144 ,  H01L21/6715 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/544 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/3701 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

公开(公告)号：US20170221800A1

公开(公告)日：2017-08-03

申请号：US15515297

申请日：2015-03-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Atsushi NISHIKIZAWA ,  Yuichi YATO ,  Hiroi OKA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/49575 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.

公开(公告)号：US20170077069A1

公开(公告)日：2017-03-16

申请号：US15211421

申请日：2016-07-15

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00 ,  H01L23/29 ,  H01L23/495 ,  H01L21/48 ,  H01L23/047 ,  H01L23/498

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0206 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

Abstract translation: 半导体器件的可靠性得到改善。 在管芯焊盘上安装第一和第二半导体芯片。 第一和第二半导体芯片和芯片焊盘的一部分被密封在密封部分中。 第一半导体芯片包括功率晶体管。 第二半导体芯片控制第一半导体芯片。 安装第一半导体芯片的芯片焊盘部分的厚度小于安装第二半导体芯片的芯片焊盘部分的厚度。

公开(公告)号：US20160093557A1

公开(公告)日：2016-03-31

申请号：US14871769

申请日：2015-09-30

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NISHIKIZAWA ,  Tadatoshi DANNO ,  Hiroyuki NAKAMURA ,  Osamu SOMA ,  Akira UEMURA

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/58 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/585 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/33505 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.

Abstract translation: 半导体器件包括第一和第二半导体芯片，多个引线，多个引线和密封这些部件的密封体。 电连接到第一和第二电极焊盘的第一焊盘电极，第二焊盘电极和内部布线形成在第一半导体芯片的主表面上。 第二半导体芯片的第三焊盘电极经由第一导线电连接到第一半导体芯片的第一电极焊盘，第一半导体芯片的第二电极焊盘经由第二导线电连接到第一引线。 第一引线和第一半导体芯片之间的距离小于第一引线和第二半导体芯片之间的距离。 第一电极焊盘，第二电极焊盘和内部布线不连接到形成在第一半导体芯片中的任何电路。

公开(公告)号：US20150084135A1

公开(公告)日：2015-03-26

申请号：US14494409

申请日：2014-09-23

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Takashi NAKAMURA ,  Tadatoshi DANNO

IPC: H01L23/538 ,  H01L27/02 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L24/09 ,  H01L23/4824 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/085 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0605 ,  H01L2224/091 ,  H01L2224/45014 ,  H01L2224/48096 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/4847 ,  H01L2224/4903 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A source interconnect and a drain interconnect are alternately provided between a plurality of transistor units. One bonding wire is connected to a source interconnect at a plurality of points. The other bonding wire is connected to a source interconnect at a plurality of points. In addition, one bonding wire is connected to a drain interconnect at a plurality of points. In addition, the other bonding wire is connected to a drain interconnect at a plurality of points.

Abstract translation: 源极互连和漏极互连交替地设置在多个晶体管单元之间。 一个接合线在多个点处连接到源互连。 另一个接合线在多个点处连接到源互连。 此外，一个接合线在多个点处连接到漏极互连。 此外，另一个接合线在多个点处连接到漏极互连。

公开(公告)号：US20150069594A1

公开(公告)日：2015-03-12

申请号：US14539479

申请日：2014-11-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO ,  Hirokazu KATO

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49513 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40091 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract translation: 可以防止半导体器件劣化。 半导体器件具有包括顶表面，底表面和多个侧表面的突片。 突片的每个侧表面具有连续到突片的底表面的第一部分，位于第一部分的外部并且延伸到突片的顶表面的第二部分，以及位于第二部分外侧的第三部分 并且延伸到突片的顶表面以面向与第一和第二部分中的每一个相同的方向。 在平面图中，半导体芯片的外边缘位于突片的第三部分和第二部分之间，并且将半导体芯片固定到突片的粘合剂材料的外边缘位于半导体芯片和第二部分之间 。