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    Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern
    12.
    发明授权
    Semiconductor device and method of balancing surfaces of an embedded PCB unit with a dummy copper pattern 有权

    公开(公告)号：US10177010B2

    公开(公告)日：2019-01-08

    申请号：US15235008

    申请日：2016-08-11

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Kang Chen ,  Hin Hwa Goh ,  Il Kwon Shim

    IPC: H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/538

    Abstract: A semiconductor device has a substrate. A conductive via is formed through the substrate. A plurality of first contact pads is formed over a first surface of the substrate. A plurality of second contact pads is formed over a second surface of the substrate. A dummy pattern is formed over the second surface of the substrate. An indentation is formed in a sidewall of the substrate. An opening is formed through the substrate. An encapsulant is deposited in the opening. An insulating layer is formed over second surface of the substrate. A dummy opening is formed in the insulating layer. A semiconductor die is disposed adjacent to the substrate. An encapsulant is deposited over the semiconductor die and substrate. The first surface of the substrate includes a width that is greater than a width of the second surface of the substrate.

    Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure
    18.
    发明授权
    Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure 有权

    公开(公告)号：US11127666B2

    公开(公告)日：2021-09-21

    申请号：US15428007

    申请日：2017-02-08

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Kang Chen ,  Jianmin Fang

    IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/31

    Abstract: A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.

    Semiconductor device and method of forming microelectromechanical systems (MEMS) package
    19.
    发明授权
    Semiconductor device and method of forming microelectromechanical systems (MEMS) package 有权

    公开(公告)号：US10662056B2

    公开(公告)日：2020-05-26

    申请号：US16169817

    申请日：2018-10-24

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Won Kyoung Choi ,  Kang Chen ,  Ivan Micallef

    IPC: B81B7/00 ,  B81C1/00 ,  H01L21/56 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00

    Abstract: A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

    Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package
    20.
    发明授权
    Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package 有权

    公开(公告)号：US10297518B2

    公开(公告)日：2019-05-21

    申请号：US15167662

    申请日：2016-05-27

    Applicant: STATS ChipPAC Pte. Ltd.

    Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/29

    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer and includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

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