公开(公告)号：US20150255358A1

公开(公告)日：2015-09-10

申请号：US14638219

申请日：2015-03-04

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/0362 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/12042 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract translation: 半导体封装包括半导体芯片，第一和第二凹陷，第一和第二再分布层和封装层。 半导体芯片具有电连接并设置在半导体芯片的上表面上的电子部件和导电焊盘。 第一凹陷部和第一再分布层从半导体芯片的上表面向下表面延伸。 第一再分配层和导电焊盘电连接。 第二凹陷和第二再分布层从下表面向上表面延伸并且通过连接部分与第一凹陷连接。 第二再分配层通过连接部分电连接到第一再分配层。 包装层设置在下表面上。

公开(公告)号：US20140073089A1

公开(公告)日：2014-03-13

申请号：US14077877

申请日：2013-11-12

Applicant: XINTEC INC.

Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG

IPC: H01L25/00

CPC classification number: H01L25/50 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/098 ,  B81C1/0023 ,  B81C2203/0109 ,  B81C2203/0792 ,  H01L21/6835 ,  H01L24/94 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A chip package includes a substrate having an upper and a lower surface and including: at least a first contact pad; a non-optical sensor chip disposed overlying the upper surface, wherein the non-optical sensor chip includes at least a second contact pad and has a first length; a protective cap disposed overlying the non-optical sensor chip, wherein the protective cap has a second length, an extending direction of the second length is substantially parallel to that of the first length, and the second length is shorter than the first length; an IC chip disposed overlying the protective cap, wherein the IC chip includes at least a third contact pad and has a third length, and an extending direction of the third length is substantially parallel to that of the first length; and bonding wires forming electrical connections between the substrate, the non-optical sensor chip, and the IC chip.

Abstract translation: 芯片封装包括具有上表面和下表面的衬底，并且包括：至少第一接触焊盘; 设置在上表面上的非光学传感器芯片，其中所述非光学传感器芯片至少包括第二接触焊盘并具有第一长度; 设置在所述非光学传感器芯片上的保护盖，其中所述保护盖具有第二长度，所述第二长度的延伸方向基本上平行于所述第一长度的延伸方向，并且所述第二长度短于所述第一长度; 设置在所述保护盖上的IC芯片，其中所述IC芯片包括至少第三接触焊盘并具有第三长度，并且所述第三长度的延伸方向基本上与所述第一长度的延伸方向平行; 以及在基板，非光学传感器芯片和IC芯片之间形成电连接的接合线。

公开(公告)号：US20170047300A1

公开(公告)日：2017-02-16

申请号：US15340909

申请日：2016-11-01

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/268

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光器停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。

公开(公告)号：US20160190063A1

公开(公告)日：2016-06-30

申请号：US14983401

申请日：2015-12-29

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/522 ,  H01L21/76 ,  H01L21/304 ,  H01L21/683 ,  H01L21/268 ,  H01L21/768 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

公开(公告)号：US20160133544A1

公开(公告)日：2016-05-12

申请号：US14869602

申请日：2015-09-29

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L21/78 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/00 ,  H01L21/268

CPC classification number: H01L21/76898 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/304 ,  H01L21/3105 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/0233 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06135 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/1411 ,  H01L2224/14181 ,  H01L2224/432 ,  H01L2224/4502 ,  H01L2224/45144 ,  H01L2924/01079 ,  H01L2924/00014

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和与第一表面相对的第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面。 隔离层和导电垫在一起具有第二通孔，使得激光阻挡件通过第二通孔露出。 再分配层位于第三表面，第二通孔的侧壁和激光停止器上。

公开(公告)号：US20150303178A1

公开(公告)日：2015-10-22

申请号：US14692613

申请日：2015-04-21

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/04

CPC classification number: H01L25/16 ,  H01L21/561 ,  H01L23/3114 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/45014 ,  H01L2224/45101 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73209 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/19011 ,  H01L2924/19105 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/206

Abstract: A chip package includes a semiconductor chip, a first chip, a first connection portion, a molding layer, a metal redistribution layer and a packaging layer. The semiconductor chip includes a first conductive pad and a second conductive pad disposed on an upper surface of the semiconductor chip. The first chip is disposed on the upper surface, and the first chip has at least a first chip conductive pad. The first connection portion directly electrically connects the first chip conductive pad and the first conductive pad. The molding layer covers the upper surface, the first chip and the first connection portion, and the molding layer is formed with an opening exposing a second conductive pad. The metal redistribution layer is disposed in the opening, electrically connected to the second conductive pad and extending to the molding layer. The packaging layer covers the metal redistribution layer and the molding layer.

Abstract translation: 芯片封装包括半导体芯片，第一芯片，第一连接部分，成型层，金属再分配层和封装层。 半导体芯片包括设置在半导体芯片的上表面上的第一导电焊盘和第二导电焊盘。 第一芯片设置在上表面上，并且第一芯片具有至少第一芯片导电焊盘。 第一连接部分直接电连接第一芯片导电焊盘和第一导电焊盘。 模制层覆盖上表面，第一芯片和第一连接部分，并且模制层形成有露出第二导电焊盘的开口。 金属再分配层设置在开口中，电连接到第二导电垫并延伸到模制层。 包装层覆盖金属再分配层和成型层。

公开(公告)号：US20150145094A1

公开(公告)日：2015-05-28

申请号：US14552186

申请日：2014-11-24

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/8385 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14335 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract translation: 提供了包括第一基板的芯片封装。 多个第一导电焊盘设置在第一基板的第一侧上。 第二基板附接到与第一基板的第一侧相对的第二侧。 第二基板包括微电元件，并且具有多个与多个第一导电焊盘相对应的第二导电焊盘，该第二导电焊盘设置在第二基板的第一侧上且位于第一基板和第二基板之间。 再分配层设置在与第二基板的第一侧相对的第二侧上。 再分配层穿透第二基板，第二导电焊盘和第一基板并延伸到第一导电焊盘中以电连接第一和第二导电焊盘。

公开(公告)号：US20140225237A1

公开(公告)日：2014-08-14

申请号：US14172832

申请日：2014-02-04

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU ,  Ying-Nan WEN

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L21/78 ,  B81B7/0064 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/11 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A chip scale package structure includes a chip, a dam unit, a board body, a plurality of first conductors, an encapsulating glue, a plurality of first conductive layers, an isolation layer, and a plurality of first electrodes. The dam unit is disposed on the surface of the chip. The board body is located on the dam unit. The first conductors are respectively in electrical contact with the conductive pads of the chip. The encapsulating glue covers the surface of the chip, and the board body and the first conductors are packaged in the encapsulating glue. The first conductive layers are located on the surface of the encapsulating glue opposite to the chip and respectively in electrical contact with the first conductors. The isolation layer is located on the encapsulating glue and the first conductive layers. The first electrodes are respectively in electrical contact with the first conductive layers.

Abstract translation: 芯片级封装结构包括芯片，堤坝单元，板体，多个第一导体，封装胶，多个第一导电层，隔离层和多个第一电极。 大坝单元设置在芯片的表面上。 板体位于坝体上。 第一导体分别与芯片的导电焊盘电接触。 封装胶覆盖芯片的表面，并且板体和第一导体封装在封装胶中。 第一导电层位于与芯片相对的封装胶的表面上，分别与第一导体电接触。 隔离层位于封装胶和第一导电层上。 第一电极分别与第一导电层电接触。

公开(公告)号：US20130193520A1

公开(公告)日：2013-08-01

申请号：US13828537

申请日：2013-03-14

Applicant: Xintec Inc.

Inventor： Baw-Ching PERNG ,  Ying-Nan WEN ,  Shu-Ming CHANG ,  Ching-Yu NI ,  Yun-Jui HSIEH ,  Wei-Ming CHEN ,  Chia-Lun TSAI ,  Chia-Ming CHENG

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/492 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/13091 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrate and the terminals.

Abstract translation: 功率MOSFET封装包括具有相反的第一和第二表面的半导体衬底，具有第一导电类型，并形成漏极区，从第一表面向下延伸并具有第二导电类型的掺杂区，掺杂区中的源极区 并且具有第一导电类型，覆盖或掩埋在第一表面下方的栅极，其中栅极电介质层位于栅极和半导体衬底之间，覆盖半导体衬底的第一导电结构，具有第一端子，并且电连接漏极 区域，覆盖半导体衬底的第二导电结构，具有第二端子，并且电连接源极区域，覆盖半导体衬底的第三导电结构，具有第三端子和电连接栅极，其中第一，第二， 并且第三端子基本上共面，并且第三端子之间的保护层 e半导体衬底和端子。

公开(公告)号：US20180175092A1

公开(公告)日：2018-06-21

申请号：US15895575

申请日：2018-02-13

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L24/19 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: A chip package is provided. The chip package includes a sensing device. The chip package also includes a first conductive structure disposed on the sensing device and electrically connected to the sensing device. The chip package further includes a chip and a second conductive structure disposed on the sensing device. The chip includes an integrated circuit device. The second conductive structure is positioned on the chip and is electrically connected to the integrated circuit device and the first conductive structure. In addition, the chip package includes an insulating layer covering the sensing device and the chip. The insulating layer has a hole. The first conductive structure is positioned under the bottom of the hole. The top surface of the insulating layer is coplanar with the top surface of the second conductive structure. A method for forming the chip package is also provided.