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    Heterogeneous compression architecture for optimized compression ratio
    265.
    发明授权
    Heterogeneous compression architecture for optimized compression ratio 有权

    公开(公告)号：US09871535B2

    公开(公告)日：2018-01-16

    申请号：US15393599

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/34 ,  H03M7/40 ,  H03M7/30

    CPC classification number: H03M7/40 ,  H03M7/30 ,  H03M7/3086

    Abstract: A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte position of the byte matches a second byte string starting from a second byte position, responsive to determining that the first byte string matches the second byte string, generate a token comprising a first symbol encoding a length of the first byte string and a second symbol encoding a byte distance between the first byte position and the second byte position, and responsive to determining that the first byte string does not match another byte string, generate the token comprising the first symbol comprising the byte and a second symbol encoding a determined value.

    TECHNOLOGIES FOR PROVIDING FILE-BASED RESILIENCY
    267.
    发明申请
    TECHNOLOGIES FOR PROVIDING FILE-BASED RESILIENCY 审中-公开

    公开(公告)号：US20170371741A1

    公开(公告)日：2017-12-28

    申请号：US15193337

    申请日：2016-06-27

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal

    IPC: G06F11/10 ,  H03M13/15 ,  H03M13/09

    CPC classification number: G06F11/1004 ,  H03M13/09 ,  H03M13/1515

    Abstract: Technologies for providing file-based data resiliency include an apparatus having a memory to store file data and a processor to manage encode or decode operations on the file data. The processor is to determine an increase in file size to be allocated for a reserved portion of a file to be stored in the memory, generate an erasure code based on content of the file and the determined increase in file size, wherein the erasure code is to facilitate decorruption of the file, and write the erasure code to the reserved portion of the file.

    Techniques for parallel data compression
    268.
    发明授权
    Techniques for parallel data compression 有权

    公开(公告)号：US09853660B1

    公开(公告)日：2017-12-26

    申请号：US15468061

    申请日：2017-03-23

    Applicant: INTEL CORPORATION

    Inventor： Vinodh Gopal ,  Kirk S. Yap ,  Daniel F. Cutter ,  James D. Guilford ,  Wajdi K. Feghali

    IPC: H03M7/00 ,  H03M7/34 ,  H03M7/30 ,  H03M7/40

    CPC classification number: H03M7/3086 ,  H03M7/40 ,  H03M7/6023

    Abstract: Techniques and apparatus for parallel data compression are described. An apparatus to provide parallel data compression may include at least one memory and logic for a compression component, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to provide at least one data input sequence to a plurality of compression components, determine compression information for the plurality of compression components, and perform a compression process on the at least one data input sequence via the plurality of compression components to generate at least one data output sequence, the plurality of compression components to perform the compression process in parallel based on the compression information.

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