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    Apparatus for electroless plating a contact pad
    272.
    发明授权
    Apparatus for electroless plating a contact pad 有权
    用于化学镀接触垫的装置

    公开(公告)号：US06451116B2

    公开(公告)日：2002-09-17

    申请号：US09920892

    申请日：2001-08-01

    Applicant: Tongbi Jiang ,  Li Li

    Inventor： Tongbi Jiang ,  Li Li

    IPC: B05C302

    CPC classification number: H01L24/05 ,  H01L21/02052 ,  H01L21/288 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/7685 ,  H01L24/03 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  Y10S134/902

    Abstract: A method and apparatus is disclosed for sequential processing of integrated circuits, particularly for conductively passivating a contact pad with a material which resists formation of resistive oxides. In particular, a tank is divided into three compartments, each holding a different solution: a lower compartment and two upper compartments divided by a barrier, which extends across and partway down the tank. The solutions have different densities and therefore separate into different layers. In the illustrated embodiment, integrated circuits with patterned contact pads are passed through one of the upper compartments, in which oxide is removed from the contact pads. Continuing downward into the lower compartment and laterally beneath the barrier, a protective layer is selectively formed on the insulating layer surrounding the contact pads. As the integrated circuits are moved upwardly into the second upper compartment, a conducting monomer selectively forms on the contact pads prior to any exposure to air. The integrated circuits can then be transferred to an ozone chamber where polymerization results in a conductive passivation layer on the contact pad.

    Abstract translation: 公开了用于集成电路的顺序处理的方法和装置，特别是用抵抗形成电阻氧化物的材料导电地钝化接触焊盘。 特别地，罐被分成三个隔室，每个隔间都有一个不同的解决方案：一个下隔室和两个隔离隔间的隔离隔板，两个隔间延伸横跨槽和一半的槽。 溶液具有不同的密度，因此分离成不同的层。 在所示实施例中，具有图案化接触焊盘的集成电路通过上隔室之一，其中氧化物从接触焊盘移除。 继续向下进入下隔室并在屏障下方横向放置，在围绕接触垫的绝缘层上选择性地形成保护层。 当集成电路向上移动到第二上隔室中时，在任何暴露于空气之前，在接触焊盘上选择性地形成导电单体。 然后可以将集成电路转移到臭氧室，其中聚合导致接触焊盘上的导电钝化层。

    Resistance-reducing conductive adhesives for attachment of electronic components
    276.
    发明授权
    Resistance-reducing conductive adhesives for attachment of electronic components 失效
    用于电子部件附着的电阻降低导电粘合剂

    公开(公告)号：US06346750B1

    公开(公告)日：2002-02-12

    申请号：US09561030

    申请日：2000-04-28

    Applicant: Tongbi Jiang ,  Whonchee Lee

    Inventor： Tongbi Jiang ,  Whonchee Lee

    IPC: H01L2348

    CPC classification number: H01L24/31 ,  C09J9/02 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2224/83886 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H05K3/321 ,  H05K3/323 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05669

    Abstract: Resistance-reducing conductive adhesives, and apparatus and methods of attaching electronic components using resistance-reducing conductive adhesives are provided. In one embodiment, a resistance-reducing conductive adhesive includes a first quantity of conductive adhesive, and a second quantity of a chelating agent combined with the conductive adhesive. The chelating agent reacts with an oxidized conductive material (e.g. alumina or aluminum ion) on a conductive lead to form soluble conductive metal-ligand complex. The chelating agent may also passivate the oxide-free conductive material by forming hydrogen bonds. The resistance of the resulting electrical connection is reduced in comparison with prior art methods of conductive adhesive coupling, providing improved signal strength, reduced power consumption, and decreased waste heat. In alternate embodiments, the conductive adhesive may include an anisotropically conductive adhesive, an isotropically conductive adhesive, a conductive epoxy, or a hydrophilic adhesive. Similarly, the conductive material may include aluminum, copper, gold, nickel, platinum or silver. Alternately, the chelating agents may be any suitable agent that provides the desired reactive mechanisms, including, for example, an oxalic acid, malonic acid, succinic acid, or citric acid. In a further embodiment, the quantity of chelating agent is a value within the range from approximately 0.1 percent by weight to approximately 20 percent by weight, inclusive. In another embodiment, an electronic assembly includes a first component having a first conductive lead, a second conductive lead, and a resistance-reducing conductive layer extending between the first and second conductive leads. The first component may be a die, a circuit board, or any other electronic component.

    Abstract translation: 提供了降低阻力的导电粘合剂，以及使用电阻降低导电粘合剂附着电子元件的装置和方法。 在一个实施方案中，电阻降低导电粘合剂包括第一量的导电粘合剂和与导电粘合剂组合的第二量的螯合剂。 螯合剂与导电引线上的氧化的导电材料（例如氧化铝或铝离子）反应形成可溶的导电金属 - 配体络合物。 螯合剂也可以通过形成氢键来钝化无氧化物的导电材料。 与现有技术的导电粘合剂耦合方法相比，所得到的电连接的电阻降低，提供改善的信号强度，降低的功率消耗和减少的废热。 在替代实施例中，导电粘合剂可以包括各向异性导电粘合剂，各向异性导电粘合剂，导电环氧树脂或亲水性粘合剂。 类似地，导电材料可以包括铝，铜，金，镍，铂或银。 或者，螯合剂可以是提供所需反应机理的任何合适的试剂，包括例如草酸，丙二酸，琥珀酸或柠檬酸。 在另一个实施方案中，螯合剂的量为约0.1重量％至约20重量％（含）范围内的值。 在另一个实施例中，电子组件包括具有第一导电引线，第二导电引线和在第一和第二导电引线之间延伸的电阻降低导电层的第一元件。 第一组件可以是模具，电路板或任何其它电子部件。

    Zero insertion force sockets using negative thermal expansion materials
    279.
    发明授权
    Zero insertion force sockets using negative thermal expansion materials 失效
    使用负热膨胀材料的零插入插座

    公开(公告)号：US06264486B1

    公开(公告)日：2001-07-24

    申请号：US09630977

    申请日：2000-08-02

    Applicant: Tongbi Jiang ,  Zhiqiang Wu

    Inventor： Tongbi Jiang ,  Zhiqiang Wu

    IPC: H01R1320

    CPC classification number: H01R12/82 ,  H01R12/58 ,  H05K1/0271 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3421 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09472 ,  Y10S439/932

    Abstract: A socket device for receiving a connection pin is disclosed, the socket device including a substrate having an upper surface. The socket device includes a connection pad disposed on the upper surface and a first layer disposed on the upper surface and on the connection pad. The first layer includes material having an overall positive coefficient of thermal expansion. The socket device includes a second layer disposed on the first layer. The second layer includes material having an overall negative coefficient of thermal expansion. The socket device also includes a contact hole formed in the first and second layers exposing a portion of the connection pad.

    Abstract translation: 公开了一种用于接收连接销的插座装置，插座装置包括具有上表面的基板。 插座装置包括设置在上表面上的连接垫和设置在上表面上和连接垫上的第一层。 第一层包括具有总体正的热膨胀系数的材料。 插座装置包括设置在第一层上的第二层。 第二层包括具有总体负的热膨胀系数的材料。 插座装置还包括形成在第一和第二层中的接触孔，露出连接垫的一部分。

    Using an organic layer as an ion implantation mask when forming shallow source/drain region
    280.
    发明授权
    Using an organic layer as an ion implantation mask when forming shallow source/drain region 有权
    当形成浅源/漏区时，使用有机层作为离子注入掩模

    公开(公告)号：US6165856A

    公开(公告)日：2000-12-26

    申请号：US133291

    申请日：1998-08-12

    Applicant: Tongbi Jiang ,  David Y. Kao

    Inventor： Tongbi Jiang ,  David Y. Kao

    IPC: H01L21/265 ,  H01L21/336

    CPC classification number: H01L29/6659 ,  H01L21/2652

    Abstract: The invention pertains to semiconductor processing methods of implanting dopants into semiconductor substrates. In one aspect, the invention includes, a semiconductor processing method comprising: a) forming an organic layer over a semiconductive substrate; and b) implanting a conductivity-enhancing dopant through the organic layer and into the semiconductive substrate. In another aspect, the invention includes a semiconductor processing method comprising: a) providing a semiconductive substrate and defining source and drain locations within so the semiconductive substrate; b) forming an organic layer over the source and drain locations; c) implanting a conductivity-enhancing dopant through the organic layer and into the source and drain locations to form source and drain implant regions within the source and drain locations, respectively; and d) forming a transistor gate proximate the source and drain implant regions. In another aspect, the invention includes a semiconductor processing method comprising: a) forming a transistor gate over a semiconductive substrate and defining source/drain locations within the semiconductive substrate proximate the transistor gate; b) forming a polyimide layer over the transistor gate and over the source/drain locations; c) depositing photoresist over the polyimide layer; d) patterning the photoresist to form openings over the source/drain locations; and e) implanting a conductivity-enhancing dopant into the openings, through the polyimide layer and into the source/drain locations.

    Abstract translation: 本发明涉及将掺杂剂注入到半导体衬底中的半导体处理方法。 一方面，本发明包括半导体处理方法，包括：a）在半导体衬底上形成有机层; 和b）通过有机层注入导电性增强掺杂剂并进入半导体衬底。 在另一方面，本发明包括一种半导体处理方法，包括：a）提供半导体衬底并限定半导电衬底内的源极和漏极位置; b）在源极和漏极位置上形成有机层; c）通过有机层注入电导率增强掺杂剂并进入源极和漏极位置，以分别在源极和漏极位置内形成源极和漏极注入区域; 以及d）在源极和漏极注入区域附近形成晶体管栅极。 在另一方面，本发明包括一种半导体处理方法，包括：a）在半导体衬底上形成晶体管栅极，并在半导体衬底附近界定晶体管栅极处的源极/漏极位置; b）在晶体管栅极上方和源极/漏极位置上形成聚酰亚胺层; c）在聚酰亚胺层上沉积光致抗蚀剂; d）图案化光致抗蚀剂以在源极/漏极位置上形成开口; 以及e）将导电性增强掺杂剂注入到开口中，通过聚酰亚胺层并进入源极/漏极位置。

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