公开(公告)号：US5643805A

公开(公告)日：1997-07-01

申请号：US401678

申请日：1995-03-10

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Hiroo Masuda ,  Yoichi Tamaki ,  Takahide Ikeda ,  Asao Nishimura ,  Takashi Hashimoto

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L23/485 ,  H01L27/06 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L23/4855 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/01 ,  Y10S148/124 ,  Y10S148/135

摘要： A bipolar device having a level difference between the contact area level of a base electrode and a base region in a silicon substrate, and the contact area level of an emitter electrode and an emitter region in the silicon substrate in the range of 0.03 .mu.m to 0.1 .mu.m by removing undesirable impurities from the emitter region and a predetermined horizontal distance between a sidewall and a device isolation film does not generate dislocation and show good electric characteristics.

摘要翻译： 具有硅基板中的基极的接触面积电平与基极区域之间的电平差的硅双极器件，以及硅基板的发射电极和发射极区域的接触面积电平为0.03μm〜 通过从发射极区域去除不需要的杂质并且侧壁和器件隔离膜之间的预定水平距离不产生位错并且显示出良好的电特性，0.1μm。

公开(公告)号：US5608265A

公开(公告)日：1997-03-04

申请号：US207697

申请日：1994-03-09

申请人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Naotaka Tanaka ,  Tetsuo Kumazawa

发明人： Makoto Kitano ,  Asao Nishimura ,  Akihiro Yaguchi ,  Nae Yoneda ,  Ryuji Kohno ,  Naotaka Tanaka ,  Tetsuo Kumazawa

IPC分类号： H01L21/56 ,  H01L23/12 ,  H01L23/13 ,  H01L23/28 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L23/02 ,  H01L29/40

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/13 ,  H01L23/4951 ,  H01L23/49541 ,  H01L25/105 ,  H01L25/16 ,  H05K1/181 ,  H05K3/3436 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H05K2201/09472 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10818 ,  H05K2201/10931 ,  H05K3/3426 ,  H05K3/3431 ,  Y02P70/611 ,  Y02P70/613

摘要： A semiconductor device, provided in a plastic encapsulated package, having a semiconductor chip, a lead and a member for electrically connecting them together. The semiconductor device has one or more first holes respectively extending from one surface of the package to a first side of the lead which is provided inside of the package, and has one or more second holes formed which are aligned with the first holes, respectively, in a manner such that each second hole is extended from the opposing surface of the package to a corresponding location on a second side of the lead and is aligned with a corresponding, opposing first hole, in the package, extending to the first side of the lead. These holes are provided as a plurality of sets of individual pairs of aligned holes respectively extending inwardly, from opposing surfaces of the package, to opposite sides of the corresponding leads. In the device the leads or the leads with resin act as partitions thereby effecting isolation between the first and second holes of each pair aligned holes.

摘要翻译： 设置在塑料封装封装中的半导体器件具有半导体芯片，引线和用于将它们电连接在一起的部件。 半导体器件具有分别从封装的一个表面延伸到设置在封装内部的引线的第一侧的一个或多个第一孔，并且分别具有与第一孔对准的一个或多个第二孔， 以使得每个第二孔从包装的相对表面延伸到引线的第二侧上的对应位置并且与包装中的相应的相对的第一孔对准，延伸到包装的第一侧 铅。 这些孔被设置为多组对齐的对齐的孔，分别从包装的相对表面向内延伸到相应引线的相对侧。 在装置中，引线或具有树脂的引线作为隔板，从而实现每对对齐的孔的第一和第二孔之间的隔离。

公开(公告)号：US5537884A

公开(公告)日：1996-07-23

申请号：US287593

申请日：1994-08-08

申请人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

发明人： Asao Nishimura ,  Naotaka Tanaka ,  Isao Hirose

IPC分类号： G01N3/00 ,  G01N3/24 ,  G01N19/04

CPC分类号： G01N3/24 ,  G01N19/04 ,  G01N2203/0066 ,  G01N2203/0091

摘要： A method for measuring an adhesion strength of a resin material which is capable of accurately and readily measuring a universal adhesion strength independent of dimensions and shapes of specimen. A delamination portion is partially formed between a resin and an adherend material. Loads in two different directions are applied to an adhering interface such that opposed shear stresses are generated. As a result, a true adhering strength can be obtained from an apparent delamination propagating strength in each case.

公开(公告)号：US5530286A

公开(公告)日：1996-06-25

申请号：US293555

申请日：1994-08-22

申请人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

发明人： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjoh ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L23/495 ,  H01L25/10 ,  H01L29/06 ,  H05K1/14 ,  H05K1/18 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L24/32 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/06136 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48799 ,  H01L2224/73215 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  Y10T29/49121

摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

公开(公告)号：US5488254A

公开(公告)日：1996-01-30

申请号：US219742

申请日：1994-03-29

申请人： Asao Nishimura ,  Makoto Kitano ,  Ichio Shimizu

发明人： Asao Nishimura ,  Makoto Kitano ,  Ichio Shimizu

IPC分类号： H01L23/28 ,  H01L23/06 ,  H01L23/29 ,  H01L23/433 ,  H01L33/64 ,  H01L23/48 ,  H01L23/02

CPC分类号： H01L23/4334 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/1815

摘要： A plastic-molded-type semiconductor device is designed to prevent interfaces of a heat conductive member for heat radiation and plastic encapsulant from being separated from each other. The device is of a structure in which the heat conductive member for heat radiation is provided on and thermally connected to one side of a semiconductor chip, and the whole chip and the whole or a part of side surfaces of the heat conductive member are covered with the resin, the opposite side of the heat conductive member being exposed. In this structure, that portion of the heat conductive member which is covered with the resin has a cross-section whose configuration is any one of a circle, an ellipse, a polygon with corner portions whose internal angle is less than 180 degrees and a dull angle or which are rounded to have a low curvature. With this structure, shearing stress which acts on the adhesion interfaces between the heat conductive member and the resin can be decreased, and also, tightening force from the resin which is exerted on the side surfaces of the heat conductive member can be made uniform, so that separation of the adhesion interfaces can be prevented.

摘要翻译： 塑料模制型半导体器件被设计成防止用于散热的热传导部件和塑料密封剂的界面彼此分离。 该装置具有这样的结构，其中用于散热的导热构件设置在半导体芯片的一侧并与其热连接，并且整个芯片和导热构件的整个或一部分侧表面被覆盖 所述树脂，所述导热构件的相对侧露出。 在该结构中，被树脂覆盖的导热部件的部分的截面形状为圆形，椭圆形，内角小于180度的角部的多边形和钝的 角度或圆形以具有低曲率。 利用这种结构，可以减小作用在导热构件和树脂之间的粘合界面上的剪切应力，并且也可以使施加在导热构件的侧表面上的树脂的紧固力均匀，因此 可以防止粘合界面的分离。

公开(公告)号：US20110140185A1

公开(公告)日：2011-06-16

申请号：US13032009

申请日：2011-02-22

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L27/06 ,  H01L27/108

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近，在这些端子处，凸起电极 （208）。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US20070241330A1

公开(公告)日：2007-10-18

申请号：US11808808

申请日：2007-06-13

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L23/48

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07247879B2

公开(公告)日：2007-07-24

申请号：US10873360

申请日：2004-06-23

申请人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

发明人： Asao Nishimura ,  Syouji Syukuri ,  Gorou Kitsukawa ,  Toshio Miyamoto

IPC分类号： H01L29/04

CPC分类号： H01L22/32 ,  G01R31/2884 ,  G01R31/31713 ,  H01L2224/02379 ,  H01L2224/0392 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

摘要翻译： 在半导体集成电路器件中，使用诸如重定位布线层（205）之类的导电层的测试焊盘（209b）位于仅用于探针检查的接合焊盘（202b）的正上方或附近， 凸起电极（208）不被设置。 甚至可以提供类似的测试焊盘相对于诸如具有凸起电极的焊盘的端子。 通过使用这些测试垫或者在与测试垫一起形成凸块电极的组合使用底部凸点冶金来执行探针测试。 根据上述，由于使用了测试垫，因此可能不会添加专用于探针测试的焊盘的凸起电极。 此外，使用设置在诸如接合焊盘的端子附近的测试焊盘并且尺寸小于凸块下的金属，使得能够在重新定位布线处理之后执行探针测试。

公开(公告)号：US07138722B2

公开(公告)日：2006-11-21

申请号：US11057495

申请日：2005-02-15

申请人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

发明人： Toshio Miyamoto ,  Asao Nishimura ,  Koki Noguchi ,  Satoshi Michishita ,  Masashi Horiguchi ,  Masaharu Kubo ,  Kazuyoshi Shiba

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L27/10897 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/16245 ,  H01L2224/451 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12033 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00 ,  H01L2924/00012

摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

公开(公告)号：US07091620B2

公开(公告)日：2006-08-15

申请号：US11116209

申请日：2005-04-28

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masnori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe ,  Takehiro Ohnishi ,  Noriou Shimada ,  Shuji Eguchi ,  Hiroshi Koyama ,  Akira Nagai ,  Masahiko Ogino

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.