公开(公告)号：US09058858B2

公开(公告)日：2015-06-16

申请号：US13303231

申请日：2011-11-23

Applicant: Hong-Chen Cheng ,  Chia-En Huang ,  Chih-Chieh Chiu ,  Jung-Ping Yang

Inventor： Hong-Chen Cheng ,  Chia-En Huang ,  Chih-Chieh Chiu ,  Jung-Ping Yang

IPC: G11C11/418 ,  G11C8/10 ,  G11C11/413

CPC classification number: G11C8/10 ,  G11C11/413 ,  G11C11/418

Abstract: An apparatus includes a level shifter and a switching circuit. The level shifter includes an input, a first output, and second output having a logic value complementary to a logic value of the first output. The switching circuit includes a data input, a feedback input coupled to the second output of the level shifter, and an output coupled to the input of the level shifter. The switching circuit is configured to selectively latch, based on a select signal, a logic state of the level shifter at the second output.

Abstract translation: 一种装置包括电平移位器和开关电路。 电平移位器包括具有与第一输出的逻辑值互补的逻辑值的输入，第一输出和第二输出。 切换电路包括数据输入，耦合到电平移位器的第二输出的反馈输入以及耦合到电平移位器的输入的输出。 开关电路被配置为基于选择信号选择性地锁存第二输出处的电平移位器的逻辑状态。

公开(公告)号：US09053989B2

公开(公告)日：2015-06-09

申请号：US13228094

申请日：2011-09-08

Applicant: Chen-Cheng Kuo ,  Chita Chuang ,  Tsung-Shu Lin ,  Chen-Shien Chen

Inventor： Chen-Cheng Kuo ,  Chita Chuang ,  Tsung-Shu Lin ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/141 ,  H01L2224/14135 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01013 ,  H01L2924/01073 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/0103 ,  H01L2924/01025 ,  H01L2924/01024 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01078 ,  H01L2924/0104 ,  H01L2924/206 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/13012 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A device includes a chip attached to a substrate. The chip includes a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a conductive trace and a mask layer overlying the conductive trace, wherein the mask layer has an opening exposing a portion of the conductive trace. An interconnection is formed between the conductive pillar and the exposed portion of the conductive trace. The opening has a first dimension (d1) measured along the long axis of the conductive pillar and a second dimension (d2) measured along the short axis of the conductive pillar. A ratio of L to d1 is greater than a ratio of W to d2.

Abstract translation: 一种器件包括附接到衬底的芯片。 该芯片包括具有沿着导电柱的长轴测量的长度（L）和沿导电柱的短轴测量的宽度（W）的导电柱。 衬底包括覆盖导电迹线的导电迹线和掩模层，其中掩模层具有暴露导电迹线的一部分的开口。 在导电柱和导电迹线的暴露部分之间形成互连。 开口具有沿着导电柱的长轴测量的第一尺寸（d1）和沿着导电柱的短轴测量的第二尺寸（d2）。 L与d1的比值大于W与d2的比。

公开(公告)号：US08982609B2

公开(公告)日：2015-03-17

申请号：US13372099

申请日：2012-02-13

Applicant: Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

Inventor： Jung-Ping Yang ,  Hong-Chen Cheng ,  Chih-Chieh Chiu ,  Chia-En Huang ,  Cheng Hung Lee

IPC: G11C11/00

CPC classification number: G11C11/4094 ,  G11C11/419

Abstract: A memory includes a first bit line, a memory cell coupled to the first bit line, and a read assist device coupled to the first bit line. The read assist device is configured to pull a first voltage on the first bit line toward a predetermined voltage in response to a first datum being read out from the memory cell. The read assist device includes a first circuit configured to establish a first current path between the first bit line and a node of the predetermined voltage during a first stage. The read assist device further includes a second circuit configured to establish a second current path between the first bit line and the node of the predetermined voltage during a second, subsequent stage.

Abstract translation: 存储器包括第一位线，耦合到第一位线的存储器单元和耦合到第一位线的读取辅助器件。 读取辅助装置被配置为响应于从存储器单元读出的第一数据，将第一位线上的第一电压拉向预定电压。 读取辅助装置包括第一电路，其被配置为在第一阶段期间在第一位线和预定电压的节点之间建立第一电流路径。 读取辅助装置还包括第二电路，其被配置为在第二后续阶段期间在第一位线和预定电压的节点之间建立第二电流路径。

公开(公告)号：US08765497B2

公开(公告)日：2014-07-01

申请号：US13225113

申请日：2011-09-02

Applicant: Hao-Juin Liu ,  Chita Chuang ,  Ching-Wen Hsiao ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen

Inventor： Hao-Juin Liu ,  Chita Chuang ,  Ching-Wen Hsiao ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Chih-Hua Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L22/20 ,  H01L22/14 ,  H01L23/3128 ,  H01L23/48 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls.

Abstract translation: 一种方法包括将多个底部单元放置在夹具上，其中多个底部单元没有锯切并形成一个集成部件。 多个底部单元中的每一个包括封装基板和结合到封装基板的管芯。 多个上部组件堆放在多个底部单元上，其中焊球位于多个上部组件和多个底部单元之间。 执行回流以通过焊球将多个上部部件堆叠与多个底部单元中的相应的底部单元接合。

公开(公告)号：US08723609B2

公开(公告)日：2014-05-13

申请号：US13558360

申请日：2012-07-26

Applicant: Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

Inventor： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

IPC: H03B5/12 ,  H03B19/14 ,  H03B27/00 ,  H03C3/22 ,  H03L7/24

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1296 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/004 ,  H03B2200/0078 ,  H03B2201/0208 ,  H03L7/24

Abstract: A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

Abstract translation: 提供了包括第一VCO单元，第二VCO单元和匹配电路的压控振荡器（VCO）模块。 第一VCO单元包括第一端子和第二端子，并产生第一振荡器信号。 第二VCO单元耦合到第一VCO单元并产生第二振荡器信号。 匹配电路耦合在第一VCO单元和第二VCO单元之间。 匹配电路包括分别耦合在第一VCO单元的第一端和第二VCO单元之间的多个电感器模块，位于第一VCO单元的第一端子和第二端子之间，并且在第一VCO单元的第二端子之间 和第二个VCO单元。 此外，还提供了一种用于产生振荡器信号的方法。

公开(公告)号：US08675439B2

公开(公告)日：2014-03-18

申请号：US13271353

申请日：2011-10-12

Applicant: Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

Inventor： Hong-Chen Cheng ,  Jung-Ping Yang ,  Chiting Cheng ,  Cheng-Hung Lee ,  Sang H. Dong ,  Hung-Jen Liao

IPC: G11C5/14

CPC classification number: G11C7/12 ,  G11C11/419

Abstract: In a digital memory with an array of bit cells coupled to word lines and bit lines, each bit cell having cross coupled inverters isolated from bit lines by passing gate transistors until addressed, some or all of the bit cells are switchable between a sleep mode and a standby mode in response to a control signal. A bit line bias circuit controls the voltage at which the bit lines are caused to float when in the sleep mode. A pull-up transistor for each bit line BL or BLB in a complementary pair has a conductive channel coupled to a positive supply voltage and a gate coupled to the other bit line in the pair, BLB or BL, respectively. A connecting transistor also can be coupled between the bit lines of the complementary pair, bringing the floating bit lines to the supply voltage less a difference voltage ΔV.

Abstract translation: 在具有耦合到字线和位线的位单元阵列的数字存储器中，每个位单元具有通过将栅极晶体管直接寻址而与位线隔离的交叉耦合的反相器，部分或全部位单元可在睡眠模式和 响应于控制信号的待机模式。 位线偏置电路控制在处于睡眠模式时使位线浮动的电压。 用于互补对中的每个位线BL或BLB的上拉晶体管具有耦合到正电源电压的导电沟道和耦合到该对BLB或BL中的另一位线的栅极。 连接晶体管也可以耦合在互补对的位线之间，使浮置位线降低到差值ΔVV的电源电压。

公开(公告)号：US20140036608A1

公开(公告)日：2014-02-06

申请号：US13776040

申请日：2013-02-25

Applicant: Chih-Chieh CHIU ,  Hong-Chen CHENG

Inventor： Chih-Chieh CHIU ,  Hong-Chen CHENG

IPC: G11C7/22

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/227 ,  G11C11/4076 ,  G11C11/4099

Abstract: A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.

Abstract translation: 信号发生电路包括第一电路，跟踪电路和与第一电路和跟踪电路耦合的延迟电路。 第一电路被配置为从延迟电路的输出接收第一时钟信号和输出信号，并且产生第二时钟信号和至少一个第一跟踪信号。 跟踪电路被配置为接收至少一个第一跟踪信号并产生第二跟踪信号。 延迟电路被配置为接收第二时钟信号和第二跟踪信号并产生输出信号。

公开(公告)号：US08604594B2

公开(公告)日：2013-12-10

申请号：US13346995

申请日：2012-01-10

Applicant: Chen-Cheng Kuo

Inventor： Chen-Cheng Kuo

IPC: H01L23/552

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/552 ,  H01L23/562 ,  H01L23/585 ,  H01L23/66 ,  H01L2223/6688 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor chip includes a through-silicon via (TSV), a device region, and a cross-talk prevention ring encircling one of the device region and the TSV. The TSV is isolated from substantially all device regions comprising active devices by the cross-talk prevention ring.

Abstract translation: 一种半导体芯片包括环形通孔（TSV），器件区域和环绕该器件区域和TSV之一的串扰防止环。 TSV通过串扰防止环从基本上包括有源设备的所有设备区域隔离。

公开(公告)号：US08598030B2

公开(公告)日：2013-12-03

申请号：US12855360

申请日：2010-08-12

Applicant: Chen-Cheng Kuo ,  Chen-Shien Chen

Inventor： Chen-Cheng Kuo ,  Chen-Shien Chen

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01061 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A process for making a copper post with footing profile employs dual photoresist films of different photosensitivities and thicknesses on an under-bump-metallurgy (UBM) layer. After an exposure lithography process, a first opening with a substantially vertical sidewall is formed in a first photoresist film, and a second opening with a sloped sidewall is formed in a second photoresist film. The second opening has a top diameter and a bottom diameter greater than the top diameter, and the bottom diameter is greater than the diameter of the first opening. A conductive layer is then formed in the first opening and the second opening followed by removing the dual photoresist films.

Abstract translation: 用于制造具有基脚轮廓的铜柱的方法使用在凸块下 - 冶金（UBM）层上具有不同光敏度和厚度的双光致抗蚀剂膜。 在曝光光刻工艺之后，在第一光致抗蚀剂膜中形成具有基本上垂直的侧壁的第一开口，并且在第二光致抗蚀剂膜中形成具有倾斜侧壁的第二开口。 第二开口具有大于顶部直径的顶部直径和底部直径，并且底部直径大于第一开口的直径。 然后在第一开口和第二开口中形成导电层，随后除去双光致抗蚀剂膜。

公开(公告)号：US08573450B2

公开(公告)日：2013-11-05

申请号：US13209829

申请日：2011-08-15

Applicant: Chih-Hua Hsu ,  Chen-Chen Cheng ,  Rui-Heng Lin

Inventor： Chih-Hua Hsu ,  Chen-Chen Cheng ,  Rui-Heng Lin

IPC: G01F11/00

CPC classification number: B05C17/0103 ,  B05C17/0116

Abstract: An electrical caulking gun has a gun body and a clutching device. The clutching device has a clutching switch, a linking lever, a clutching block and a block spring. The clutching switch is mounted on the gun body and has a pressed segment and a pushing segment having an inclined pushing surface. The linking lever is pivotally mounted in the gun body and has an abutting end and a pushing end. The abutting end abuts with the pushing surface of the clutching switch. The clutching block has an inclined pushed surface and an engaging rod. The engaging rod detachably engages a transmission device of the caulking gun. The block spring provides a force to push the engaging rod on the clutching block to engage the transmission device.

Abstract translation: 电气铆接枪具有枪体和离合器。 该离合装置具有夹紧开关，连接杆，紧固块和块弹簧。 夹紧开关安装在枪体上，并具有压入段和具有倾斜推动表面的推动段。 连接杆可旋转地安装在枪体中并且具有邻接端和推动端。 抵接端与紧固开关的推动表面相接。 离合器具有倾斜的推动表面和接合杆。 接合杆可拆卸地接合铆接枪的传动装置。 块弹簧提供力以将接合杆推动在离合块上以接合传动装置。