公开(公告)号：US08610283B2

公开(公告)日：2013-12-17

申请号：US12573183

申请日：2009-10-05

申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Ian D. Melville ,  Krystyna Waleria Semkow

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/02697 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05007 ,  H01L2224/05016 ,  H01L2224/05026 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05187 ,  H01L2224/05562 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/15787 ,  H01L2924/04953 ,  H01L2924/01014 ,  H01L2224/05552 ,  H01L2924/00

摘要： Disclosed is a semiconductor device wherein an insulation layer has a copper plug in contact with the last wiring layer of the device. There may also be a barrier layer separating the copper plug from the insulation layer. In a further embodiment, there may also be an aluminum layer between the insulation layer and copper plug. Also disclosed is a process for making the semiconductor device.

摘要翻译： 公开了一种半导体器件，其中绝缘层具有与器件的最后布线层接触的铜插塞。 还可以存在将铜塞与绝缘层分离的阻挡层。 在另一实施例中，在绝缘层和铜插塞之间也可以有铝层。 还公开了制造半导体器件的方法。

公开(公告)号：US08563416B2

公开(公告)日：2013-10-22

申请号：US13194616

申请日：2011-07-29

申请人： Brian Michael Erwin ,  Ian D. Melville ,  Ekta Misra ,  George John Scott

发明人： Brian Michael Erwin ,  Ian D. Melville ,  Ekta Misra ,  George John Scott

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03616 ,  H01L2224/03848 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13111 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2224/11912 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

摘要： A solder bump support structure and method of manufacturing thereof is provided. The solder bump support structure includes an inter-level dielectric (ILD) layer formed over a silicon substrate. The ILD layer has a plurality of conductive vias. The structure further includes a first insulation layer formed on the ILD layer. The solder bump support structure further includes a pedestal member formed on the ILD layer which includes a conductive material formed above the plurality of conductive vias in the ILD layer coaxially surrounded by a second insulation layer. The second insulation layer is thicker than the first insulation layer. The structure further includes a capping under bump metal (UBM) layer formed over, and in electrical contact with, the conductive material and formed over at least a portion of the second insulation layer of the pedestal member.

摘要翻译： 提供焊料凸块支撑结构及其制造方法。 焊料凸块支撑结构包括在硅衬底上形成的级间电介质（ILD）层。 ILD层具有多个导电通孔。 该结构还包括形成在ILD层上的第一绝缘层。 焊料凸块支撑结构还包括形成在ILD层上的基座构件，其包括形成在由第二绝缘层同轴围绕的ILD层中的多个导电通孔上方的导电材料。 第二绝缘层比第一绝缘层厚。 该结构还包括形成在导电材料之上并与导电材料电接触并且形成在基座构件的第二绝缘层的至少一部分上的封盖凸块下金属（UBM）层。

公开(公告)号：US08486814B2

公开(公告)日：2013-07-16

申请号：US13187917

申请日：2011-07-21

申请人： Jennifer C. Clark ,  Emily R. Kinser ,  Ian D. Melville ,  Candace A. Sullivan

发明人： Jennifer C. Clark ,  Emily R. Kinser ,  Ian D. Melville ,  Candace A. Sullivan

IPC分类号： H01L21/265 ,  H01L21/306

CPC分类号： H01L21/311 ,  H01L21/0209 ,  H01L21/30604 ,  H01L21/30608 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

摘要： A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices.

摘要翻译： 晶片和制造方法包括包括用于制造半导体器件的衬底的基底结构。 底座结构包括形成半导体器件的前侧和与前侧相对的后侧。 在基底结构的背面形成一个集成层，其中包括被配置为改变相对于基底结构的蚀刻选择性的杂质，使得集成层可选择性地从基底结构移除，以消除半导体器件的制造过程中产生的缺陷。

公开(公告)号：US08236615B2

公开(公告)日：2012-08-07

申请号：US12625590

申请日：2009-11-25

申请人： Alexandre Blander ,  Jon A Casey ,  Timothy H Daubenspeck ,  Ian D Melville ,  Jennifer V Muncy ,  Marie-Claude Paquet

发明人： Alexandre Blander ,  Jon A Casey ,  Timothy H Daubenspeck ,  Ian D Melville ,  Jennifer V Muncy ,  Marie-Claude Paquet

IPC分类号： H01L21/00

CPC分类号： H01L23/295 ,  H01L21/563 ,  H01L23/3142 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material.

摘要翻译： 公开了一种其制造方法。 该结构包括具有悬浮在其中的固体的有机钝化层。 优选蚀刻去除一部分有机材料并暴露这些固体的部分产生增强的表面粗糙度，这提供了关于该钝化层与包装底部填充材料的粘附性的显着优点。

公开(公告)号：US20110147922A1

公开(公告)日：2011-06-23

申请号：US12640752

申请日：2009-12-17

申请人： Raschid J. BEZAMA ,  Timothy H. DAUBENSPECK ,  Gary LaFONTANT ,  Ian D. MELVILLE ,  Ekta MISRA ,  George J. SCOTT ,  Krystyna W. SEMKOW ,  Timothy D. SULLIVAN ,  Robin A. SUSKO ,  Thomas A. WASSICK ,  Xiaojin WEI ,  Steven L. WRIGHT

发明人： Raschid J. BEZAMA ,  Timothy H. DAUBENSPECK ,  Gary LaFONTANT ,  Ian D. MELVILLE ,  Ekta MISRA ,  George J. SCOTT ,  Krystyna W. SEMKOW ,  Timothy D. SULLIVAN ,  Robin A. SUSKO ,  Thomas A. WASSICK ,  Xiaojin WEI ,  Steven L. WRIGHT

IPC分类号： H01L23/498 ,  H01L21/3205

CPC分类号： H01L23/49816 ,  H01L21/76804 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05094 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Structures and methods to reduce maximum current density in a solder ball are disclosed. A method includes forming a contact pad in a last wiring level and forming a plurality of wires of the contact pad extending from side edges of the contact pad to respective ones of a plurality of vias. Each one of the plurality of wires has substantially the same electrical resistance.

摘要翻译： 公开了减少焊球中的最大电流密度的结构和方法。 一种方法包括在最后的布线层中形成接触焊盘，并且形成从接触焊盘的侧边缘延伸到多个通孔中的多个通孔的接触焊盘的多个导线。 多个导线中的每一根具有基本上相同的电阻。

公开(公告)号：US07732932B2

公开(公告)日：2010-06-08

申请号：US11833348

申请日：2007-08-03

申请人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

发明人： Peter J. Brofman ,  Jon Alfred Casey ,  Ian D. Melville ,  David L. Questad ,  Wolfgang Sauter ,  Thomas Anthony Wassick

IPC分类号： H01L23/492

CPC分类号： H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

摘要： Structures and a method for forming the same. The structure includes a semiconductor substrate, a transistor on the semiconductor substrate, and N interconnect layers on top of the semiconductor substrate, N being a positive integer. The transistor is electrically coupled to the N interconnect layers. The structure further includes a first dielectric layer on top of the N interconnect layers and P crack stop regions on top of the first dielectric layer, P being a positive integer. The structure further includes a second dielectric layer on top of the first dielectric layer. Each crack stop region of the P crack stop regions is completely surrounded by the first dielectric layer and the second dielectric layer. The structure further includes an underfill layer on top of the second dielectric layer. The second dielectric layer is sandwiched between the first dielectric layer and the underfill layer.

摘要翻译： 结构及其形成方法。 该结构包括半导体衬底，半导体衬底上的晶体管和半导体衬底顶部的N个互连层，N为正整数。 晶体管电耦合到N个互连层。 该结构还包括在N个互连层的顶部上的第一介电层和在第一介电层的顶部上的P个裂纹停止区，P是正整数。 该结构还包括在第一电介质层的顶部上的第二电介质层。 P裂纹停止区域的每个裂纹停止区域被第一介电层和第二介电层完全包围。 该结构还包括在第二电介质层的顶部上的底部填充层。 第二电介质层夹在第一介电层和底部填充层之间。

公开(公告)号：US07573115B2

公开(公告)日：2009-08-11

申请号：US11559130

申请日：2006-11-13

申请人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

发明人： Ian D. Melville ,  Mukta G. Farooq ,  Dae Young Jung

IPC分类号： H01L23/52

CPC分类号： H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/02351 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced.

摘要翻译： 本发明提供了半导体集成电路和芯片封装之间的接合焊盘结构，其具有增强的抗断裂性和改进的可靠性。 在粘结结构中使用的材料之间的温度膨胀系数（CTE）的不匹配会对其造成应力和剪切，这可能导致后端介质堆叠中的断裂，并导致包装的可靠性问题。 通过设置通过多个金属通孔连接到接合焊盘的多个金属焊盘，增强了接合焊盘和后端电介质叠层之间的粘附力。

公开(公告)号：US20090039515A1

公开(公告)日：2009-02-12

申请号：US11836819

申请日：2007-08-10

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L23/5329 ,  H01L23/556 ,  H01L2924/0002 ,  Y10S438/958 ,  Y10S438/967 ,  H01L2924/00

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.

摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。

公开(公告)号：US20080057677A1

公开(公告)日：2008-03-06

申请号：US11470355

申请日：2006-09-06

申请人： Sylvie Charles ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Robert Hannon ,  Ian D. Melville ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Sylvie Charles ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Robert Hannon ,  Ian D. Melville ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L21/78 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L24/16 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Chip location identification using dummy solder bead(s) is disclosed. A structure may include an integrated circuit (IC) chip including a plurality of solder beads for electrically coupling the IC chip to other structure, and a chip location identifier including at least one dummy solder bead on the IC chip, the chip location identifier representing a unique location of the IC chip in a wafer prior to dicing. The structure allows location tracking of an IC chip within a wafer without any additional processing, space, or mask levels. The structure can also be evaluated (visually or electrically) at the packaging level.

摘要翻译： 公开了使用虚拟焊珠的芯片位置识别。 结构可以包括集成电路（IC）芯片，其包括用于将IC芯片电耦合到其他结构的多个焊料珠，以及包括IC芯片上的至少一个虚拟焊珠的芯片位置标识符，芯片位置标识符表示 IC芯片在切割之前在晶片中的独特位置。 该结构允许在晶片内的IC芯片的位置跟踪，而没有任何额外的处理，空间或掩模级别。 还可以在包装层面评估（视觉或电气）结构。

公开(公告)号：US10784200B2

公开(公告)日：2020-09-22

申请号：US13409643

申请日：2012-03-01

申请人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

发明人： Mukta G. Farooq ,  Ian D. Melville ,  Kevin S. Petrarca ,  Kenneth P. Rodbell

IPC分类号： H01L23/532 ,  H01L23/556

摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.