公开(公告)号：US11984396B2

公开(公告)日：2024-05-14

申请号：US18089213

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/05 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US10595409B2

公开(公告)日：2020-03-17

申请号：US15628430

申请日：2017-06-20

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC: H01L25/00 ,  H05K1/14 ,  H01L23/552 ,  H01L23/13 ,  H01L23/498 ,  H05K1/02 ,  H01L25/065 ,  H05K3/36

Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

公开(公告)号：US09859253B1

公开(公告)日：2018-01-02

申请号：US15196937

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Saikumar Jayaraman ,  John S. Guzek ,  Yidnekachew S. Mekonnen

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/76838 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/85815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161

Abstract: Apparatuses, methods and systems associated with integrated circuit (IC) package design are disclosed herein. An IC package stack may include a first IC package and a second IC package. The first IC package may include a first die and a first redistribution layer that communicatively couples contacts on the first side of the first IC package to the first die and to contacts on a second side of the first IC package, the second side opposite to the first side. The second IC package may be mounted to the second side of the first IC package. The second IC package may include a second die and a second redistribution layer that communicatively couples contacts on a side of the second IC package to the second die, the contacts of the second IC package communicatively coupled to the contacts on the second side of the first IC package.

公开(公告)号：US09847234B2

公开(公告)日：2017-12-19

申请号：US14614687

申请日：2015-02-05

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.

公开(公告)号：US09820384B2

公开(公告)日：2017-11-14

申请号：US14102676

申请日：2013-12-11

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Robert L. Sankman ,  Charles Gealer ,  Omkar Karhade ,  John S. Guzek ,  Ravi V. Mahajan ,  James C. Matayabas, Jr. ,  Johanna Swan ,  Feras Eid ,  Shawna Liff ,  Timothy McIntosh ,  Telesphor Kamgaing ,  Adel Elsherbini ,  Kemal Aygun

IPC: H05K1/18 ,  H05K13/04 ,  H01L23/00 ,  H05K1/03 ,  G06F1/16 ,  H01L21/56

CPC classification number: H05K1/189 ,  G06F1/163 ,  H01L21/568 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H05K1/0393 ,  H05K1/181 ,  H05K1/185 ,  H05K13/0469 ,  H05K2201/0137 ,  H05K2203/1469 ,  Y10T29/49146 ,  H01L2924/00

Abstract: This disclosure relates generally to devices, systems, and methods for making a flexible microelectronic assembly. In an example, a polymer is molded over a microelectronic component, the polymer mold assuming a substantially rigid state following the molding. A routing layer is formed with respect to the microelectronic component and the polymer mold, the routing layer including traces electrically coupled to the microelectronic component. An input is applied to the polymer mold, the polymer mold transitioning from the substantially rigid state to a substantially flexible state upon application of the input.

公开(公告)号：US20170290155A1

公开(公告)日：2017-10-05

申请号：US15628430

申请日：2017-06-20

Applicant: INTEL CORPORATION

Inventor： Adel A. Elsherbini ,  Ravindranath Mahajan ,  John S. Guzek ,  Nitin A. Deshpande

IPC: H05K1/14 ,  H01L25/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/552 ,  H01L25/065

CPC classification number: H05K1/147 ,  H01L23/13 ,  H01L23/49833 ,  H01L23/552 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K3/361 ,  H05K2201/09245 ,  H05K2201/09681 ,  Y10T29/49126

Abstract: Embodiments of the present disclosure are directed towards electro-magnetic interference (EMI) shielding techniques and configurations. In one embodiment, an apparatus includes a first substrate, a die having interconnect structures coupled with the first substrate to route input/output (I/O) signals between the die and the first substrate and a second substrate coupled with the first substrate, wherein the die is disposed between the first substrate and the second substrate and at least one of the first substrate and the second substrate include traces configured to provide electro-magnetic interference (EMI) shielding for the die. Other embodiments may be described and/or claimed.

公开(公告)号：US20170287831A1

公开(公告)日：2017-10-05

申请号：US15620555

申请日：2017-06-12

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravindranath V. Mahajan

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US09780054B2

公开(公告)日：2017-10-03

申请号：US14529881

申请日：2014-10-31

Applicant: INTEL CORPORATION

Inventor： John S. Guzek ,  Javier Soto Gonzalez ,  Nicholas R. Watts ,  Ravi K Nalla

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/03 ,  H01L25/10 ,  H05K1/18 ,  H01L21/768 ,  H01L25/07 ,  H01L23/31 ,  H01L25/11 ,  H05K3/46

CPC classification number: H01L24/11 ,  H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/768 ,  H01L23/315 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/26 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/03 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2221/68345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/11831 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24145 ,  H01L2224/24227 ,  H01L2224/26 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92132 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/40252 ,  H01L2924/40407 ,  H01L2924/40501 ,  H05K1/185 ,  H05K3/4682 ,  H05K2201/10477 ,  H05K2203/0152 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Embodiments of the present invention describe a semiconductor package having an embedded die. The semiconductor package comprises a coreless substrate that contains the embedded die. The semiconductor package provides die stacking or package stacking capabilities. Furthermore, embodiments of the present invention describe a method of fabricating the semiconductor package that minimizes assembly costs.

公开(公告)号：US09686870B2

公开(公告)日：2017-06-20

申请号：US14566198

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Weng Hong Teh ,  John S. Guzek

IPC: H05K3/32 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683

CPC classification number: H05K3/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68372 ,  H01L2224/32245 ,  H01L2224/82001 ,  H01L2224/82002 ,  H01L2224/92244 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18162 ,  Y10T29/49117 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.

公开(公告)号：US09646851B2

公开(公告)日：2017-05-09

申请号：US15070968

申请日：2016-03-15

Applicant: Intel Corporation

Inventor： Robert L. Sankman ,  John S. Guzek

IPC: H01L21/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/64 ,  H01L25/16 ,  H01L21/50 ,  H01L23/522 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/4853 ,  H01L21/31053 ,  H01L21/50 ,  H01L21/56 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/64 ,  H01L24/16 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.