公开(公告)号：US20060027934A1

公开(公告)日：2006-02-09

申请号：US11242221

申请日：2005-10-03

申请人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

发明人： Daniel Edelstein ,  Paul Andry ,  Leena Buchwalter ,  Jon Casey ,  Sherif Goma ,  Raymond Horton ,  Gareth Hougham ,  Michael Lane ,  Xiao Liu ,  Chirag Patel ,  Edmund Sprogis ,  Michelle Steen ,  Brian Sundlof ,  Cornelia Tsang ,  George Walker ,  Yu-Ting Cheng ,  Kenneth Ocheltree ,  Robert Montoye

IPC分类号： H01L23/48

CPC分类号： H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

摘要翻译： 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US20050227449A1

公开(公告)日：2005-10-13

申请号：US10709039

申请日：2004-04-08

申请人： William Murphy ,  Edmund Sprogis ,  Anthony Stamper ,  Erick Walton

发明人： William Murphy ,  Edmund Sprogis ,  Anthony Stamper ,  Erick Walton

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L29/76

CPC分类号： H01L28/20 ,  H01L27/0802 ,  Y10T29/49082 ,  Y10T29/49085

摘要： A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.

摘要翻译： 公开了一种在集成电路内制造自补偿电阻器的方法。 自补偿电阻器包括第一电阻器和第二电阻器。 初始形成具有第一电阻值的第一电阻器，然后形成具有第二电阻值的第二电阻器。 第二个电阻与第一个电阻串联。 第二电阻值小于第一电阻值，但是第一和第二电阻器的总电阻值超过期望的目标电阻范围。 最后，向第二电阻器发送电流以改变第二电阻器的尺寸，使得第一和第二电阻器的总电阻值落在期望的目标电阻范围内。

公开(公告)号：US20050127500A1

公开(公告)日：2005-06-16

申请号：US10732015

申请日：2003-12-10

申请人： Evan Colgan ,  Claudis Feger ,  Gary Goth ,  George Katopis ,  John Magerlein ,  Edmund Sprogis

发明人： Evan Colgan ,  Claudis Feger ,  Gary Goth ,  George Katopis ,  John Magerlein ,  Edmund Sprogis

IPC分类号： H01L23/34 ,  H01L21/50 ,  H01L21/56 ,  H01L23/10 ,  H01L23/12 ,  H01L23/36 ,  H01L23/367 ,  H01L23/373

CPC分类号： H01L23/367 ,  H01L23/3737 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： In an integrated circuit packaging structure, such as in an MCM or in a SCM, a compliant thermally conductive material is applied between a heat-generating integrated circuit chip and a substrate attached thereto. Raised regions are defined on the back side of the chip aligned to areas of a higher than average power density on the front active surface of the chip such that a thinner layer of the compliant thermally conductive material is disposed between the chip and the substrate in this area after assembly thereof resulting in a reduced “hot-spot” temperature on the chip. In an exemplary embodiment, the substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.

摘要翻译： 在诸如在MCM或SCM中的集成电路封装结构中，在发热集成电路芯片和附着于其之间的衬底之间施加兼容的导热材料。 凸起区域被限定在芯片的背面上，与芯片的前活性表面上的高于平均功率密度的区域相对准，使得在该芯片和衬底之间设置较薄的柔性导热材料层 组装后的区域导致芯片上的“热点”温度降低。 在示例性实施例中，基板包括散热器，冷却板，散热器，热管，散热帽，封装盖或其它冷却构件中的一个。

公开(公告)号：US20100263913A1

公开(公告)日：2010-10-21

申请号：US12424001

申请日：2009-04-15

申请人： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

发明人： Timothy H. Daubenspeck ,  Wolfgang Sauter ,  Timothy D. Sullivan ,  Steven L. Wright ,  Edmund Sprogis

IPC分类号： H05K1/00

CPC分类号： H01L24/03 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05022 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05098 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05552

摘要： In one embodiment, a sub-pad assembly of metal structures is located directly underneath a metal pad. The sub-pad assembly includes an upper level metal line structure abutting the metal pad, a lower level metal line structure located underneath the upper level metal line structure, and a set of metal vias that provide electrical connection between the lower level metal line structure located underneath the upper level metal line structure. In another embodiment, the reliability of a C4 ball is enhanced by employing a metal pad structure having a set of integrated metal vias that are segmented and distributed to facilitate uniform current density distribution within the C4 ball. The area1 density of the cross-sectional area in the plurality of metal vias is higher at the center portion of the metal pad than at the peripheral portion of the planar portion of the metal pad.

摘要翻译： 在一个实施例中，金属结构的子垫组件位于金属垫的正下方。 子焊盘组件包括邻接金属焊盘的上层金属线结构，位于上层金属线结构下方的下层金属线结构，以及一组在下层金属线结构之间提供电连接的金属通孔 在上层金属线结构下方。 在另一个实施例中，C4球的可靠性通过使用具有一组集成金属通孔的金属焊盘结构而被增强，所述集成金属通孔被分段和分配以便于在C4球内均匀的电流密度分布。 多个金属通孔中的截面积的面积1密度在金属垫的中心部分比在金属垫的平面部分的周边部分高。

公开(公告)号：US20070267746A1

公开(公告)日：2007-11-22

申请号：US11383595

申请日：2006-05-16

申请人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

发明人： Kerry Bernstein ,  Timothy Dalton ,  Timothy Harrison Daubenspeck ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Sprogis ,  Anthony Kendall Stamper

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L24/10 ,  H01L23/13 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15787 ,  H05K1/145 ,  H05K3/222 ,  H05K2201/10674 ,  Y10T436/171538 ,  Y10T436/172307 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic device and method of packaging an electronic device. The device including: a first substrate, a second substrate and an integrated circuit chip having a first side and an opposite second side, a first set of chip pads on the first side and a second set of chip pads on the second side of the integrated circuit chip, chip pads of the first set of chip pads physically and electrically connected to corresponding substrate pads on the first substrate and chip pads of the second set of chip pads physically and electrically connected to substrate pads of the substrate.

摘要翻译： 一种电子装置和包装电子装置的方法。 该装置包括：第一基板，第二基板和具有第一侧和相对的第二侧的集成电路芯片，在第一侧上的第一组芯片焊盘和在集成的第二侧上的第二组芯片焊盘 电路芯片，第一组芯片焊盘的芯片焊盘物理和电连接到第一衬底上的对应衬底焊盘，并且第二组芯片焊盘的芯片焊盘物理和电连接到衬底的衬底焊盘。

公开(公告)号：US20070077752A1

公开(公告)日：2007-04-05

申请号：US11243882

申请日：2005-10-04

申请人： Steven Codding ,  Timothy Krywanczyk ,  Edmund Sprogis ,  Jocelyn Sylvestre ,  Matthew Whalen

发明人： Steven Codding ,  Timothy Krywanczyk ,  Edmund Sprogis ,  Jocelyn Sylvestre ,  Matthew Whalen

IPC分类号： H01L21/4763 ,  G03C5/00

CPC分类号： H01L21/67132 ,  H01L21/02057 ,  H01L21/67028

摘要： A method for the removal of residual UV radiation-sensitive adhesive from the surfaces of semiconductor wafers, remaining thereon from protective UV radiation-sensitive tapes which were stripped from the semiconductor wafers. Moreover, provided is an arrangement for implementing the removal of residual sensitive adhesive, which remain from tapes employed as protective layers on semiconductor wafers, particularly wafers having surfaces including C4 connections.

摘要翻译： 从半导体晶片剥离的保护性紫外线辐射敏感带保留在其上的半导体晶片的表面上去除残留的UV辐射敏感性粘合剂的方法。 此外，提供了一种用于实现从半导体晶片上用作保护层的带留下的残留敏感性粘合剂的去除，特别是具有包括C4连接的表面的晶片的布置。

公开(公告)号：US20070035030A1

公开(公告)日：2007-02-15

申请号：US11201572

申请日：2005-08-11

申请人： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

发明人： Raymond Horton ,  John Knickerbocker ,  Edmund Sprogis ,  Cornelia Tsang

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US20070029045A1

公开(公告)日：2007-02-08

申请号：US11533609

申请日：2006-10-17

申请人： Timothy Krywanczyk ,  Edmund Sprogis

发明人： Timothy Krywanczyk ,  Edmund Sprogis

IPC分类号： H01L21/306

CPC分类号： H01L21/78

摘要： In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.

摘要翻译： 根据上述目的和优点，本发明提供了可在制造过程的磨削操作期间使用的制造装置。 该制造装置包括插座板，该插座板包括形成在其中的多个空腔，其位置和数量与形成在产品晶片的前表面上的焊料（或其他导电材料）凸起相对应。

公开(公告)号：US20060273438A1

公开(公告)日：2006-12-07

申请号：US11145423

申请日：2005-06-03

申请人： Brent Anderson ,  Edmund Sprogis

发明人： Brent Anderson ,  Edmund Sprogis

IPC分类号： H01L23/02 ,  H01L21/00

CPC分类号： H01L23/585 ,  H01L23/576 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/48227 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit layer. A second semiconductor chip includes a second circuit layer and at least one second interconnection element disposed on a second chip surface. The at least one second interconnection element is electrically coupled to the second circuit layer. The at least one first interconnection element is connected to the at least one second interconnection element to establish electrical continuity between the first circuit layer and the second circuit layer. The first surface is adjoined to the second surface. At least one ring delay circuit includes a first ring delay path partially disposed on the first circuit layer and a second ring delay path partially disposed on the second circuit layer. The first ring delay path and the second ring delay path form a signal path having a predetermined measurement signature. The ring delay circuit compares the predetermined measurement signature to a test measurement signature.

公开(公告)号：US06949458B2

公开(公告)日：2005-09-27

申请号：US10361228

申请日：2003-02-10

申请人： Edward W. Conrad ,  Chung H. Lam ,  Dale W. Martin ,  Edmund Sprogis

发明人： Edward W. Conrad ,  Chung H. Lam ,  Dale W. Martin ,  Edmund Sprogis

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

摘要： A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

摘要翻译： 用于形成具有接触焊盘的侧壁图像传送导体的方法和结构包括形成绝缘体以包括凹部，在绝缘体周围沉积导体，并蚀刻导体以形成侧壁图像传输导体，其中导体保留在凹部 并且形成接触焊盘，并且凹部垂直于侧壁图像传送导体。