公开(公告)号：US20130260551A1

公开(公告)日：2013-10-03

申请号：US13903164

申请日：2013-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Un-Byoung Kang ,  Kwang-chul Choi ,  Jung-Hwan Kim ,  Tae Hong Min ,  Hojin Lee ,  Minseung Yoon

IPC: H01L21/48

CPC classification number: H01L21/4835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02166 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/024 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03602 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06138 ,  H01L2224/06181 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented.

Abstract translation: 在半导体器件中，有机绝缘图案设置在第一和第二重新布线图案之间。 有机绝缘图案可以吸收当第一和第二重新布线图案在加热下膨胀时发生的物理应力。 由于有机绝缘图案设置在第一和第二重新布线图案之间，所以可以相对于其中在重新布线图案之间设置半导体图案的半导体器件来增加绝缘性能。 此外，由于在第一和第二重新布线图案和有机绝缘图案之间以及基板和有机绝缘图案之间设置种子层图案，所以第一和第二布线图案的粘合强度提高。 这也减少了分层问题。 此外，种子层图案防止形成重新布线图案的金属扩散到有机绝缘图案。 因此，可以实现具有增强的可靠性的半导体器件。

公开(公告)号：US11521987B2

公开(公告)日：2022-12-06

申请号：US17195756

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/00 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US20200176467A1

公开(公告)日：2020-06-04

申请号：US16516756

申请日：2019-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Sung-Gil Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim ,  Woo-Sung Lee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A vertical memory device may include a channel connecting pattern on a substrate, gate electrodes spaced apart from each other in a first direction on the channel connecting pattern, and a channel extending in the first direction through the gate electrodes and the channel connecting pattern. Each of the electrodes may extend in a second direction substantially parallel to an upper surface of the substrate, and the first direction may be substantially perpendicular to the upper surface of the substrate. An end portion of the channel connecting pattern in a third direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction may have an upper surface higher than an upper surface of other portions of the channel connecting pattern except for a portion thereof adjacent the channel.

公开(公告)号：US09875918B2

公开(公告)日：2018-01-23

申请号：US14788783

申请日：2015-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Dong Jung ,  Jung-Hwan Kim ,  Dong-Gil Lee ,  Tae-Je Cho ,  Kwang-Chul Choi

IPC: B32B43/00 ,  H01L21/67 ,  B32B38/10 ,  B32B41/00

CPC classification number: H01L21/67115 ,  B32B38/10 ,  B32B41/00 ,  B32B43/006 ,  B32B2250/02 ,  B32B2310/0843 ,  B32B2457/14 ,  H01L21/67092 ,  H01L21/67253 ,  H01L2221/68381 ,  H01L2224/98 ,  Y10T156/1158 ,  Y10T156/1917

Abstract: Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

公开(公告)号：US20160155838A1

公开(公告)日：2016-06-02

申请号：US15006522

申请日：2016-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Hun-Hyeoung Leam ,  Tae-Hyun Kim ,  Seok-Woo Nam ,  Hyun Namkoong ,  Yong-Seok Kim ,  Tea-Kwang Yu

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/28282 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/1079 ,  H01L29/42352 ,  H01L29/66818 ,  H01L29/66833 ,  H01L29/7851 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.

公开(公告)号：US11967623B2

公开(公告)日：2024-04-23

申请号：US17388233

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Jung-Hwan Kim ,  Gukhyon Yon

IPC: H01L29/423 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H01L29/42344 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/32 ,  H01L25/0652 ,  H01L25/0657 ,  H01L29/42328 ,  H01L2224/08146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Disclosed is a semiconductor device comprising gate stack structures on a substrate, separation structures extending in a first direction on the substrate and separating the gate stack structures, and vertical structures penetrating the gate stack structures. Each gate stack structure includes cell dielectric layers and electrodes including upper electrodes, a barrier layer extending between the electrodes and the cell dielectric layers, a separation dielectric pattern extending in the first direction and penetrating the upper electrodes to separate each upper electrode into pieces that are spaced apart from each other in a second direction intersecting the first direction, and capping patterns between the separation dielectric pattern and the upper electrodes. The capping patterns are on sidewalls of each upper electrode and spaced apart from each other in a third direction perpendicular to a top surface of the substrate. Each capping pattern is on a sidewall of the barrier layer.

公开(公告)号：US11910607B2

公开(公告)日：2024-02-20

申请号：US17881707

申请日：2022-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/04 ,  H01L29/792 ,  H01L29/423 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L29/04 ,  H01L29/42344 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.

公开(公告)号：US11728246B2

公开(公告)日：2023-08-15

申请号：US17331951

申请日：2021-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunggil Kim ,  Jinhyuk Kim ,  Jung-Hwan Kim

IPC: H01L29/78 ,  H01L23/48 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/481 ,  H01L25/0652 ,  H01L29/7827 ,  H10B41/27 ,  H10B43/27 ,  H01L2225/06541

Abstract: A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.

公开(公告)号：US11626414B2

公开(公告)日：2023-04-11

申请号：US16903026

申请日：2020-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunggil Kim ,  Sungjin Kim ,  Seulye Kim ,  Jung-Hwan Kim ,  Chan-Hyoung Kim

IPC: H01L27/11568 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11582 ,  G11C5/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. A semiconductor memory device includes a stack structure that includes a plurality of electrodes and a plurality of dielectric layers that are alternately stacked on a substrate, a vertical channel structure that penetrates the stack structure, and a conductive pad on the vertical channel structure. The vertical channel structure includes a semiconductor pattern and a vertical dielectric layer between the semiconductor pattern and the electrodes. An upper portion of the semiconductor pattern includes an impurity region that includes a halogen element. The upper portion of the semiconductor pattern is adjacent to the conductive pad.

公开(公告)号：US11424264B2

公开(公告)日：2022-08-23

申请号：US16838586

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Hwan Kim ,  Sunggil Kim ,  Dongkyum Kim ,  Seulye Kim ,  Ji-Hoon Choi

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/04 ,  H01L27/11565 ,  H01L29/792 ,  H01L27/11573 ,  H01L29/423 ,  H01L27/1157

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a first source conductive pattern comprising a polycrystalline material including first crystal grains on a substrate, the substrate may comprising a polycrystalline material including second crystal grains, a grain size of the first crystal grains being smaller than a grain size of the second crystal grains, a stack including a plurality of gate electrodes, the plurality of gates stacked on the first source conductive pattern, and a vertical channel portion penetrating the stack and the first source conductive pattern, and the vertical channel portion being in contact with a side surface of the first source conductive pattern.