专利检索 ap:("Taiwan Semiconductor Manufacturing Company, Ltd.") AND inv:"Yu-Jen Tseng" 第 3 页

21.

发明授权
Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices 有权

公开(公告)号：US10153243B2

公开(公告)日：2018-12-11

申请号：US15497408

申请日：2017-04-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Jen Tseng , Yen-Liang Lin , Tin-Hao Kuo , Chen-Shien Chen , Mirng-Ji Lii

IPC分类号： H01L23/00 , H01L23/528 , H01L23/498 , H01L23/488 , H01L21/44 , H01L21/47 , H01L21/283 , H01L21/02 , H01L21/027 , H01L25/065 , H01L23/31 , H01L21/56

摘要： Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. A method of forming a device includes forming a conductive trace over a first substrate, the conductive trace having first tapering sidewalls, forming a conductive bump over a second substrate, the conductive bump having second tapering sidewalls and a first surface distal the second substrate, and attaching the conductive bump to the conductive trace via a solder region. The solder region extends from the first surface of the conductive bump to the first substrate, and covers the first tapering sidewalls of the conductive trace. The second tapering sidewalls of the conductive bump are free of the solder region.

22.

发明授权
Structures having a tapering curved profile and methods of making same 有权

公开(公告)号：US10008459B2

公开(公告)日：2018-06-26

申请号：US13734811

申请日：2013-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pei-Chun Tsai , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen

IPC分类号： H01L21/44 , H01L23/00 , H01L21/768 , H01L21/48 , H01L23/498

摘要： An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap.

23.

发明授权
Interconnection structure 有权

公开(公告)号：US09673125B2

公开(公告)日：2017-06-06

申请号：US13664176

申请日：2012-10-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hao-Juin Liu , Yao-Chun Chuang , Chita Chuang , Yu-Jen Tseng , Chen-Shien Chen

IPC分类号： H01L23/48 , H01L23/31 , H01L23/29 , H01L23/00

CPC分类号： H01L23/3192 , H01L23/293 , H01L23/562 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05005 , H01L2224/05022 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05558 , H01L2224/05572 , H01L2224/1145 , H01L2224/11462 , H01L2224/13017 , H01L2224/13022 , H01L2224/13147 , H01L2924/00014 , H01L2924/206

摘要： A structure comprises a first passivation layer formed over a substrate, a second passivation layer formed over the first passivation layer, wherein the second passivation layer includes a first opening with a first dimension, a bond pad embedded in the first passivation layer and the second passivation layer, a protection layer formed on the second passivation layer comprising a second opening with a second dimension, wherein the second dimension is greater than the first dimension and a connector formed on the bond pad.

24.

发明授权
Interconnection structure and method of forming same 有权
标题翻译：互连结构及其形成方法

公开(公告)号：US09496233B2

公开(公告)日：2016-11-15

申请号：US13744361

申请日：2013-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Wei Lin , Sheng-Yu Wu , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen

IPC分类号： H01L23/00 , H01L21/768 , H01L21/48 , H01L23/498

CPC分类号： H01L24/02 , H01L21/4853 , H01L21/76885 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02125 , H01L2224/02141 , H01L2224/02145 , H01L2224/0215 , H01L2224/0401 , H01L2224/05114 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/10125 , H01L2224/11013 , H01L2224/11019 , H01L2224/1112 , H01L2224/11462 , H01L2224/11472 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13023 , H01L2224/13026 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13551 , H01L2224/13564 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13686 , H01L2224/1369 , H01L2224/14051 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/81007 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/8181 , H01L2224/81895 , H01L2224/8192 , H01L2224/81948 , H01L2225/06513 , H01L2924/04941 , H01L2924/07025 , H01L2924/181 , H01L2924/301 , H01L2924/35 , Y10T29/49144 , H01L2924/00014 , H01L2924/014 , H01L2924/05432 , H01L2924/053 , H01L2924/00 , H01L2924/00012

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion.

摘要翻译： 轨迹（BOT）结构上的实施例凸点包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下冶金（UBM）特征，安装在凸块下金属特征上的金属梯形凸起，金属梯形凸起具有第一锥形轮廓和安装在基底上的基底迹线，所述基底迹线具有第二锥形轮廓，并通过直接的金属 - 金属接合耦合到所述金属梯形凸起。可以以类似的方式制造实施例的芯片到芯片结构。

25.

发明授权
Methods for metal bump die assembly 有权
标题翻译：金属凸块模具组装方法

公开(公告)号：US08853002B2

公开(公告)日：2014-10-07

申请号：US13734644

申请日：2013-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiu-Jen Lin , Ai-Tee Ang , Yu-Jen Tseng , Yu-Peng Tsai , Ming-Da Cheng , Chung-Shi Liu

IPC分类号： H01L21/00 , H01L23/00

CPC分类号： H01L24/81 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/97 , H01L2224/0345 , H01L2224/0401 , H01L2224/05647 , H01L2224/10152 , H01L2224/1132 , H01L2224/11422 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/11602 , H01L2224/1161 , H01L2224/1182 , H01L2224/11823 , H01L2224/11825 , H01L2224/11848 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13387 , H01L2224/13582 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/75101 , H01L2224/75253 , H01L2224/7526 , H01L2224/75263 , H01L2224/75266 , H01L2224/7598 , H01L2224/81001 , H01L2224/81007 , H01L2224/81024 , H01L2224/81222 , H01L2224/81224 , H01L2224/8123 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2924/0541 , H01L2224/81 , H01L2924/00

摘要： Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

摘要翻译： 组装金属凸块的方法。在一个实施例中，一种方法包括提供具有多个导电端子的集成电路管芯; 沉积焊料以在导电端子上形成焊料沉积; 提供在用于接收所述集成电路裸片的表面上具有管芯附着区域的衬底，所述衬底具有形成在所述管芯附着区域中的多个导电迹线; 对准集成电路管芯和衬底并使多个导电端子和导电迹线接触，使得焊料沉积物物理接触导电迹线; 并且将集成电路管芯和导电端子选择性地加热到足以使焊料沉积物熔化和回流的温度，在衬底上的导电迹线和集成电路管芯上的导电端子之间形成焊接连接。公开了用于选择性加热的各种能量源。

26.

发明申请
Methods for Metal Bump Die Assembly 有权
标题翻译：金属凸块组装方法

公开(公告)号：US20140193952A1

公开(公告)日：2014-07-10

申请号：US13734644

申请日：2013-01-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsiu-Jen Lin , Ai-Tee Ang , Yu-Jen Tseng , Yu-Peng Tsai , Ming-Da Cheng , Chung-Shi Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/81 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/75 , H01L24/97 , H01L2224/0345 , H01L2224/0401 , H01L2224/05647 , H01L2224/10152 , H01L2224/1132 , H01L2224/11422 , H01L2224/1146 , H01L2224/11462 , H01L2224/1147 , H01L2224/11602 , H01L2224/1161 , H01L2224/1182 , H01L2224/11823 , H01L2224/11825 , H01L2224/11848 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13387 , H01L2224/13582 , H01L2224/13583 , H01L2224/13644 , H01L2224/13655 , H01L2224/13664 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/75101 , H01L2224/75253 , H01L2224/7526 , H01L2224/75263 , H01L2224/75266 , H01L2224/7598 , H01L2224/81001 , H01L2224/81007 , H01L2224/81024 , H01L2224/81222 , H01L2224/81224 , H01L2224/8123 , H01L2224/81424 , H01L2224/81444 , H01L2224/81447 , H01L2224/81455 , H01L2224/81464 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01047 , H01L2924/01029 , H01L2924/0105 , H01L2924/0541 , H01L2224/81 , H01L2924/00

摘要： Methods for assembling metal bump dies. In an embodiment, a method includes providing an integrated circuit die having a plurality of conductive terminals; depositing solder to form solder depositions on the conductive terminals; providing a substrate having a die attach region on a surface for receiving the integrated circuit die, the substrate having a plurality of conductive traces formed in the die attach region; aligning the integrated circuit die and the substrate and bringing the plurality of conductive terminals and the conductive traces into contact, so that the solder depositions physically contact the conductive traces; and selectively heating the integrated circuit die and the conductive terminals to a temperature sufficient to cause the solder depositions to melt and reflow, forming solder connections between the conductive traces on the substrate and the conductive terminals on the integrated circuit die. Various energy sources are disclosed for the selective heating.

摘要翻译： 组装金属凸块的方法。在一个实施例中，一种方法包括提供具有多个导电端子的集成电路管芯; 沉积焊料以在导电端子上形成焊料沉积; 提供在用于接收所述集成电路裸片的表面上具有管芯附着区域的衬底，所述衬底具有形成在所述管芯附着区域中的多个导电迹线; 对准集成电路管芯和衬底并使多个导电端子和导电迹线接触，使得焊料沉积物物理接触导电迹线; 并且将集成电路管芯和导电端子选择性地加热到足以使焊料沉积物熔化和回流的温度，在衬底上的导电迹线和集成电路管芯上的导电端子之间形成焊接连接。公开了用于选择性加热的各种能量源。