公开(公告)号：US20170147857A1

公开(公告)日：2017-05-25

申请号：US15358011

申请日：2016-11-21

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: G06K9/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/52 ,  H01L21/56

Abstract: A method for forming a chip package is provided. The method includes providing a device substrate including a sensing device and conductive pads that are exposed from a surface of the device substrate. The method further includes forming a conductive structure correspondingly on each of the conductive pads, and then covering the surface of the device substrate with a hard coating layer that completely covers the respective conductive structures on the conductive pads. The method further includes thinning the hard coating layer to expose the respective conductive structures on the conductive pads. The hard coating layer and the respective conductive structures on the conductive pads have substantially planar surfaces that are level with each other. A chip package is also provided.

公开(公告)号：US20160372445A1

公开(公告)日：2016-12-22

申请号：US15164660

申请日：2016-05-25

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L23/492 ,  H01L21/48 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/3128 ,  H01L23/492 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L27/14618 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/16235

Abstract: A chip package is provided. The chip package includes a substrate having conductive pads therein and adjacent to a first surface thereof. Chips are attached on a second surface opposite to the first surface of the substrate, and an encapsulation layer covers the chips. First redistribution layers are disposed between the second surface of the substrate and the encapsulation layer, and second redistribution layers are disposed on the encapsulation layer. First conductive structures and second conductive structures are disposed in the encapsulation layer. Each of first and second conductive structures respectively includes at least one bonding ball. The first conductive structures are configured to connect first and second redistribution layers, and the second conductive structures are configured to connect the second redistribution layers and the chip. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括其中具有导电焊盘并且与其第一表面相邻的衬底。 芯片附着在与基板的第一表面相对的第二表面上，并且封装层覆盖芯片。 第一再分配层设置在衬底的第二表面和封装层之间，第二再分布层设置在封装层上。 第一导电结构和第二导电结构设置在封装层中。 第一和第二导电结构中的每一个分别包括至少一个结合球。 第一导电结构被配置为连接第一和第二再分配层，并且第二导电结构被配置为连接第二再分布层和芯片。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20160133588A1

公开(公告)日：2016-05-12

申请号：US14931633

申请日：2015-11-03

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L21/311 ,  H01L21/78 ,  H01L21/02 ,  H01L21/683 ,  H01L21/31

CPC classification number: H01L24/09 ,  G06F21/32 ,  H01L21/02013 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/08235 ,  H01L2224/08237 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad in the first though hole. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface, and has a second though hole to expose the laser stopper. The redistribution layer is located on the third surface, a sidewall of the second though hole, and the laser stopper in the second though hole. The conductive structure is located on the redistribution.

Abstract translation: 芯片封装包括芯片，激光器停止器，隔离层，再分布层，绝缘层和导电结构。 芯片具有导电焊盘，第一表面和第二表面。 导电垫位于第一表面上。 第二表面具有第一通孔以暴露导电垫。 激光停止器位于第一通孔中的导电垫上。 隔离层位于第二表面和第一通孔中。 隔离层具有与第二表面相对的第三表面，并且具有第二通孔以暴露激光制动器。 再分配层位于第三表面，第二通孔的侧壁和第二通孔中的激光停止件。 导电结构位于再分配上。

公开(公告)号：US20150325557A1

公开(公告)日：2015-11-12

申请号：US14709216

申请日：2015-05-11

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Ying-Nan WEN ,  Chien-Hung LIU ,  Wei-Chung YANG

IPC: H01L25/16 ,  H01L23/00 ,  H01L27/146 ,  H01L25/00 ,  H01L21/56 ,  H01L23/522 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3157 ,  H01L23/5226 ,  H01L24/08 ,  H01L24/17 ,  H01L24/20 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/16 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48465 ,  H01L2224/73209 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/146 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2924/00

Abstract: A chip package including a first substrate is provided. The first substrate includes a sensing device. A second substrate is attached onto the first substrate and includes an integrated circuit device. A first conductive structure is electrically connected to the sensing device and the integrated circuit device through a redistribution layer disposed on the first substrate. An insulating layer covers the first substrate, the second substrate and the redistribution layer. The insulating layer has a hole therein and a second conductive structure is disposed under the bottom of the hole. A method for forming the chip package is also provided.

Abstract translation: 提供了包括第一基板的芯片封装。 第一基板包括感测装置。 第二基板附着在第一基板上并且包括集成电路装置。 第一导电结构通过设置在第一基板上的再分配层电连接到感测装置和集成电路装置。 绝缘层覆盖第一基板，第二基板和再分布层。 绝缘层在其中具有孔，并且第二导电结构设置在孔的底部下方。 还提供了一种用于形成芯片封装的方法。

公开(公告)号：US20150287659A1

公开(公告)日：2015-10-08

申请号：US14676671

申请日：2015-04-01

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L23/31 ,  H01L21/50 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L21/02

CPC classification number: H01L23/3114 ,  G01K1/00 ,  G01L19/0627 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/3185 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L2021/60022 ,  H01L2224/02371 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/11 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A chip package is provided. The chip package includes a substrate having a first surface and a second surface opposite thereto. The substrate includes a sensing device and a conducting pad therein. The sensing device and the conducting pad are adjacent to the first surface. The conducting pad has a sidewall laterally protruding from a sidewall of the substrate. An encapsulation layer is attached to the first surface of the substrate to cover the sensing device and the conducting pad. A redistribution layer is disposed on the second surface of the substrate and extends to contact the sidewall of the conducting pad. An end of the redistribution layer protrudes from the first surface of the substrate and is level with a third surface of the encapsulation layer that is opposite to the first surface. A method of forming the chip package is also provided.

Abstract translation: 提供芯片封装。 芯片封装包括具有第一表面和与其相对的第二表面的基板。 基板包括感测装置和导电垫。 感测装置和导电垫与第一表面相邻。 导电垫具有从衬底的侧壁侧向突出的侧壁。 封装层附接到基板的第一表面以覆盖感测装置和导电垫。 再分配层设置在衬底的第二表面上并延伸以接触导电焊盘的侧壁。 再分布层的一端从衬底的第一表面突出并且与封装层的与第一表面相对的第三表面平齐。 还提供了一种形成芯片封装的方法。

公开(公告)号：US20150255358A1

公开(公告)日：2015-09-10

申请号：US14638219

申请日：2015-03-04

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Ho-Yin YIU

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/3114 ,  H01L21/268 ,  H01L21/31053 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/3185 ,  H01L23/481 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/034 ,  H01L2224/0362 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/12042 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2924/20645 ,  H01L2924/20646 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.

Abstract translation: 半导体封装包括半导体芯片，第一和第二凹陷，第一和第二再分布层和封装层。 半导体芯片具有电连接并设置在半导体芯片的上表面上的电子部件和导电焊盘。 第一凹陷部和第一再分布层从半导体芯片的上表面向下表面延伸。 第一再分配层和导电焊盘电连接。 第二凹陷和第二再分布层从下表面向上表面延伸并且通过连接部分与第一凹陷连接。 第二再分配层通过连接部分电连接到第一再分配层。 包装层设置在下表面上。

公开(公告)号：US20130130444A1

公开(公告)日：2013-05-23

申请号：US13734796

申请日：2013-01-04

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L27/14618 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/3512 ,  H01L2924/00

Abstract: The invention is related to a chip package including: a semiconductor substrate having at least one bonding pad region and at least one device region, wherein the semiconductor substrate includes a plurality of heavily doped regions in the bonding pad region, and two of the heavily doped regions are insulatively isolated; a plurality of conductive pad structures disposed over the bonding pad region; at least one opening disposed at a sidewall of the chip package to expose the heavily doped regions; and a conductive pattern disposed in the opening to electrically contact with the heavily doped region.

Abstract translation: 本发明涉及一种芯片封装，其包括：具有至少一个焊盘区域和至少一个器件区域的半导体衬底，其中半导体衬底在焊盘区域中包括多个重掺杂区域，以及两个重掺杂 区域绝对隔离; 设置在所述焊盘区域上方的多个导电焊盘结构; 设置在所述芯片封装的侧壁处的至少一个开口以暴露所述重掺杂区域; 以及设置在所述开口中以与所述重掺杂区域电接触的导电图案。

公开(公告)号：US20170278769A1

公开(公告)日：2017-09-28

申请号：US15618054

申请日：2017-06-08

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L23/31 ,  G06F21/32 ,  G06K9/00 ,  G01L19/14 ,  G01L19/06 ,  H05K3/32 ,  H01L23/29 ,  G01L19/00 ,  H05K1/18 ,  H05K1/11 ,  H01L21/02 ,  H05K1/02

CPC classification number: H01L23/3192 ,  G01L19/0061 ,  G01L19/06 ,  G01L19/14 ,  G06F21/32 ,  G06K9/00 ,  G06K9/00006 ,  H01L21/0212 ,  H01L21/02263 ,  H01L21/56 ,  H01L23/291 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/525 ,  H01L2021/60022 ,  H01L2224/11 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/181 ,  H05K3/32

Abstract: A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a conducting structure. A conducting pad and a sensing device of the chip are located on a first surface of a substrate of the chip, and the conducting pad protrudes from the side surface of the substrate. The dam layer surrounds the sensing device. The permanent adhesive layer is between the support and the substrate. The support and the permanent adhesive layer have a trench to expose the conducting pad. The buffer layer is located on the support. The redistribution layer is located on the buffer layer and on the support, the permanent adhesive layer, and the conducting pad facing the trench. The passivation layer covers the redistribution layer, the buffer layer, and the conducting pad.

公开(公告)号：US20170110641A1

公开(公告)日：2017-04-20

申请号：US15394464

申请日：2016-12-29

Applicant: XINTEC INC.

Inventor： Chien-Hung LIU

IPC: H01L35/08 ,  H01L27/146 ,  H01L35/34 ,  H01L21/78 ,  H01L35/10

CPC classification number: H01L35/08 ,  G01J5/024 ,  G01J5/045 ,  G01J5/20 ,  H01L21/78 ,  H01L23/053 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/33 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14687 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/1876 ,  H01L35/02 ,  H01L35/10 ,  H01L35/34 ,  H01L2224/11

Abstract: A semiconductor package includes a substrate, at lest one support, a cover, and a plate. The substrate has at least one light sensor or thermal sensor, a first surface, and a second surface opposite to the first surface. The light sensor or the thermal sensor is disposed on the first surface. The second surface has an opening to expose the light sensor (or the thermal sensor). The support is disposed on the first surface. The cover is disposed on the support, such that the cover is above the light sensor (or the thermal sensor) to form a first space between the cover and the light sensor (or the thermal sensor). The plate is placed on the second surface to cover the opening, such that a second space is formed between the plate and the light sensor (or the thermal sensor).

公开(公告)号：US20170047300A1

公开(公告)日：2017-02-16

申请号：US15340909

申请日：2016-11-01

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Chien-Hung LIU ,  Shih-Yi LEE ,  Ho-Yin YIU

IPC: H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/768 ,  H01L23/48 ,  H01L21/268

CPC classification number: H01L24/02 ,  H01L21/268 ,  H01L21/304 ,  H01L21/31127 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76 ,  H01L21/76802 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L27/14678 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/03002 ,  H01L2224/0311 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光器停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。