公开(公告)号：US20240234365A1

公开(公告)日：2024-07-11

申请号：US18613954

申请日：2024-03-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-Yu Chen ,  Chia-Shen Cheng ,  Hao-Jan Pei ,  Philip Yu-Shuan Chung ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/81 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/49822 ,  H01L24/17 ,  H01L2224/175 ,  H01L2224/81224 ,  H01L2924/3511

摘要： A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

公开(公告)号：US20180240719A1

公开(公告)日：2018-08-23

申请号：US15953581

申请日：2018-04-16

申请人： Qorvo US, Inc.

发明人： Alexandre Christian Volatier ,  Guillermo Moreno Granado

IPC分类号： H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/544

CPC分类号： H01L22/14 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/544 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/17104 ,  H01L2224/175 ,  H01L2224/81001 ,  H01L2224/81052 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079

摘要： Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

公开(公告)号：US20180012856A1

公开(公告)日：2018-01-11

申请号：US15202195

申请日：2016-07-05

申请人： Avago Technologies General IP (Singapore) Pte. Ltd

发明人： Deog Soon Choi ,  Ah Ron Lee ,  Hyon Mo Ku

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L24/09 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/03828 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/0912 ,  H01L2224/0951 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/1183 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13007 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/1411 ,  H01L2224/1712 ,  H01L2224/175 ,  H01L2224/81192 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81815 ,  H05K3/34 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A semiconductor package and methods for producing the same are described. One example of the semiconductor package is described to include a substrate having a first face and an opposing second face. The package is further described to include a plurality of pads disposed on the first face of the substrate, each of the plurality of pads including a first face and an opposing second face that is in contact with the first face of the substrate. The semiconductor package is further described to include a plurality of solder-on-pad structures provided on a first of the plurality of pads.

公开(公告)号：US20170256467A1

公开(公告)日：2017-09-07

申请号：US15357465

申请日：2016-11-21

申请人： Qorvo US, Inc.

发明人： Alexandre Christian Volatier ,  Guillermo Moreno Granado

IPC分类号： H01L21/66 ,  H01L23/544 ,  H01L21/78 ,  H01L23/00

CPC分类号： H01L22/14 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/544 ,  H01L24/09 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/17104 ,  H01L2224/175 ,  H01L2224/81001 ,  H01L2224/81052 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079

摘要： Methods of fabricating semiconductor devices and Radio Frequency (RF) components are provided. The method includes providing a circuit layout on a semiconductor layer and providing one or more sacrificial connections to connect bump pads in the circuit layout. The method also includes testing the circuit layout using the one or more sacrificial connections and removing at least a portion of the one or more sacrificial connections. In this way, the performance of the semiconductor device is improved by reducing or avoiding capacitive or inductive leakage paths that can be caused by leftover materials.

公开(公告)号：US20170141067A1

公开(公告)日：2017-05-18

申请号：US15419934

申请日：2017-01-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin

IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/175 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

公开(公告)号：US20170141066A1

公开(公告)日：2017-05-18

申请号：US15290131

申请日：2016-10-11

申请人： Murata Manufacturing Co., Ltd.

发明人： Yuji TOYOTA

IPC分类号： H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC分类号： H01L24/17 ,  H01L23/29 ,  H01L23/31 ,  H01L23/3107 ,  H01L23/3121 ,  H01L2021/60022 ,  H01L2224/1703 ,  H01L2224/175 ,  H01L2924/0002 ,  H01L2924/141 ,  H01L2924/142 ,  H03H9/0576 ,  H03H9/059 ,  H03H9/1085 ,  H01L2924/00012

摘要： An electronic device includes a mount board, first and second electronic components flip-chip mounted on a surface of the mount board with bumps interposed therebetween, and a sealing member that seals the first and second electronic components on the mount board. A thickness of the first electronic component is larger than a thickness of the second electronic component, and a height of the bump bonded to the first electronic component is smaller than a height of the bump bonded to the second electronic component.

公开(公告)号：US09559072B2

公开(公告)日：2017-01-31

申请号：US14803950

申请日：2015-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jing-Cheng Lin

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/17 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05082 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/116 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/175 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

摘要： A structure comprises a first semiconductor chip with a first metal bump and a second semiconductor chip with a second metal bump. The structure further comprises a solder joint structure electrically connecting the first semiconductor chip and the second semiconductor chip, wherein the solder joint structure comprises an intermetallic compound region between the first metal bump and the second metal bump, wherein the intermetallic compound region is with a first height dimension and a surrounding portion formed along exterior walls of the first metal bump and the second metal bump, wherein the surrounding portion is with a second height dimension, and wherein the second height dimension is greater than the first height dimension.

摘要翻译： 一种结构包括具有第一金属凸块的第一半导体芯片和具有第二金属凸块的第二半导体芯片。 所述结构还包括电连接所述第一半导体芯片和所述第二半导体芯片的焊接结构，其中所述焊点结构包括在所述第一金属凸块和所述第二金属凸块之间的金属间化合物区域，其中所述金属间化合物区域具有第一 高度尺寸和沿着第一金属凸块和第二金属凸块的外壁形成的周围部分，其中周围部分具有第二高度尺寸，并且其中第二高度尺寸大于第一高度尺寸。

公开(公告)号：US20160351530A1

公开(公告)日：2016-12-01

申请号：US15232525

申请日：2016-08-09

申请人： Micron Technology, Inc.

发明人： Jaspreet S. Gandhi ,  Luke G. England ,  Owen R. Fay

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/11822 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/14134 ,  H01L2224/1601 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/16505 ,  H01L2224/1701 ,  H01L2224/17181 ,  H01L2224/175 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29309 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32054 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/3301 ,  H01L2224/33505 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81125 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2224/81948 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3841 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/00012

摘要： Semiconductor devices and device packages include at least one semiconductor die electrically coupled to a substrate through a plurality of conductive structures. The at least one semiconductor die may be a plurality of memory dice, and the substrate may be a logic die. An underfill material disposed between the at least one semiconductor die and the substrate may include a thermally conductive material. An electrically insulating material is disposed between the plurality of conductive structures and the underfill material. Methods of attaching a semiconductor die to a substrate, such as for forming semiconductor device packages, include covering or coating at least an outer side surface of conductive structures, electrically coupling the semiconductor die to the substrate with an electrically insulating material, and disposing a thermally conductive material between the semiconductor die and the substrate.

摘要翻译： 半导体器件和器件封装包括通过多个导电结构电耦合到衬底的至少一个半导体管芯。 所述至少一个半导体管芯可以是多个存储器管芯，并且所述衬底可以是逻辑管芯。 设置在至少一个半导体管芯和衬底之间的底部填充材料可以包括导热材料。 电绝缘材料设置在多个导电结构和底部填充材料之间。 将半导体管芯附着到诸如用于形成半导体器件封装的衬底的方法包括覆盖或涂覆导电结构的至少外侧表面，用电绝缘材料将半导体管芯电耦合到衬底，并且设置热 导电材料在半导体管芯和衬底之间。

公开(公告)号：US09343436B2

公开(公告)日：2016-05-17

申请号：US14511051

申请日：2014-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Li Hsiao ,  Li-Yen Lin ,  Chih-Hang Tung

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/44 ,  H01L23/473 ,  H01L23/00 ,  H01L23/053 ,  F28D15/02 ,  H01L23/34 ,  H01L25/16 ,  H01L23/31 ,  H05K7/20 ,  G06F1/20

CPC分类号： H01L25/0657 ,  F28D15/02 ,  H01L23/053 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/473 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/175 ,  H01L2224/17515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/01029 ,  H01L2924/0715 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/014

摘要： A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

摘要翻译： 堆叠的封装包括衬底和结合到衬底的第一结构。 第一结构具有多个凸块，第一亲水涂层位于第一结构的侧壁上。 堆叠的封装还包括结合到多个凸块的第二结构。 第一亲水涂层位于第二结构的侧壁上。 第一结构在第二结构和衬底之间。 堆叠的包装还包括壳体，其中壳体限定包围第一结构和第二结构的体积。 第二亲水涂层位于壳体内表面的侧壁上。 堆叠的包装还包括在包围第一结构和第二结构的体积内的冷却流体。 冷却流体的顶表面在第二结构的顶表面之上。

公开(公告)号：US20150021755A1

公开(公告)日：2015-01-22

申请号：US14511051

申请日：2014-10-09

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Li HSIAO ,  Li-Yen LIN ,  Chih-Hang TUNG

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/44 ,  H01L23/473 ,  H01L23/00 ,  H01L23/053

CPC分类号： H01L25/0657 ,  F28D15/02 ,  H01L23/053 ,  H01L23/3185 ,  H01L23/34 ,  H01L23/473 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17183 ,  H01L2224/175 ,  H01L2224/17515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/01029 ,  H01L2924/0715 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/014

摘要： A stacked package includes a substrate, and a first structure bonded to the substrate. The first structure has a plurality of bumps, and a first hydrophilic coating is on sidewalls of the first structure. The stacked package further includes a second structure bonded to the plurality of bumps. The first hydrophilic coating is on sidewalls of the second structure. The first structure is between the second structure and the substrate. The stacked package further includes a housing, wherein the housing defines a volume enclosing the first structure and the second structure. A second hydrophilic coating is on sidewalls of an inner surface of the housing. The stacked package further includes a cooling fluid within the volume enclosing the first structure and the second structure. A top surface of the cooling fluid is above a top surface of the second structure.

摘要翻译： 堆叠的封装包括衬底和结合到衬底的第一结构。 第一结构具有多个凸块，第一亲水涂层位于第一结构的侧壁上。 堆叠的封装还包括结合到多个凸块的第二结构。 第一亲水涂层位于第二结构的侧壁上。 第一结构在第二结构和衬底之间。 堆叠的包装还包括壳体，其中壳体限定包围第一结构和第二结构的体积。 第二亲水涂层位于壳体内表面的侧壁上。 堆叠的包装还包括在包围第一结构和第二结构的体积内的冷却流体。 冷却流体的顶表面在第二结构的顶表面之上。