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公开(公告)号：US09693468B2
公开(公告)日：2017-06-27
申请号：US14846991
申请日：2015-09-07
Applicant: Subtron Technology Co., Ltd.
Inventor： Chih-Hong Chuang , Chien-Hung Wu
IPC: H05K3/00 , H05K3/40 , H01K1/00 , H05K3/46 , H01L21/48 , H01L21/683 , H05K1/02 , H05K1/09 , H05K1/11 , H05K3/18 , H01L23/498
CPC classification number: H05K1/09 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2221/68345 , H01L2221/68381 , H05K1/0298 , H05K1/115 , H05K3/0026 , H05K3/0047 , H05K3/007 , H05K3/18 , H05K3/205 , H05K3/4038 , H05K3/421 , H05K3/4638 , H05K3/4644 , H05K3/4682 , H05K2201/09509 , H05K2203/03
Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.
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公开(公告)号：US20170176804A1
公开(公告)日：2017-06-22
申请号：US15356058
申请日：2016-11-18
Inventor： Jihun CHOI , Jae-Eun PI
IPC: G02F1/1345 , H01L23/00 , H01L27/12
CPC classification number: G02F1/13458 , H01L23/498 , H01L24/05 , H01L24/06 , H01L24/14 , H01L24/16 , H01L24/17 , H01L27/124 , H01L2224/0401 , H01L2224/05025 , H01L2224/06102 , H01L2224/1403 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/81447 , H05K1/113 , H05K2201/094 , H05K2201/09509 , H05K2201/09672 , H05K2201/10659 , H05K2201/10674 , H01L2924/00014
Abstract: Provided is display panel including a substrate including a pixel area and a pad area; and a first conductive line and a second conductive line stacked on the substrate, wherein the first conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area and the second conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area. The first part of the first conductive line and the first part of the second conductive line are parallel to each other and the second part of the first conductive line and the second part of the second conductive line are overlapped vertically.
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公开(公告)号：US09684237B2
公开(公告)日：2017-06-20
申请号：US14817378
申请日：2015-08-04
Applicant: International Business Machines Corporation
Inventor： Hiroyuki Mori , Hirokazu Noma , Keishi Okamoto
CPC classification number: G03F7/0035 , G03F7/38 , H05K3/428 , H05K3/4679 , H05K2201/09509 , H05K2201/09563 , H05K2201/09845 , H05K2203/0577 , H05K2203/0588 , H05K2203/1453
Abstract: A method of forming a circuit board includes forming a conductive pattern on a substrate; forming a first negative resist on the substrate after formation of the conductive pattern; partially exposing the first negative resist on the surface of the conductive pattern to form a first via exposure portion; forming a second negative resist on the substrate after formation of the first via exposure portion; partially exposing the second negative resist on the first via exposure portion to form a second via exposure portion larger than the first via exposure portion; developing the first negative resist and the second negative resist after formation of the second via exposure portion to form a via opening reaching the conductive pattern; and filling the via opening with a conductive material.
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24.发明申请公开(公告)号：US20170156208A1
公开(公告)日：2017-06-01
申请号：US15431781
申请日：2017-02-14
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
IPC: H05K1/11 , H01L23/00 , H01L23/498 , H05K1/18 , H05K1/05
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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25.发明授权公开(公告)号：US09668345B2
公开(公告)日：2017-05-30
申请号：US14389387
申请日：2013-03-27
Applicant: HITACHI CHEMICAL COMPANY, LTD.
Inventor： Hiroyuki Yamaguchi , Seiichi Kurihara , Hiroshi Sakurai , Shunsuke Nukina
CPC classification number: H05K1/116 , H05K1/0216 , H05K1/0218 , H05K1/0251 , H05K1/0298 , H05K1/115 , H05K3/0047 , H05K3/429 , H05K3/4611 , H05K2201/0154 , H05K2201/09509 , H05K2201/09518 , H05K2201/09545 , H05K2201/0959 , H05K2201/09854 , H05K2201/10287 , H05K2203/061 , H05K2203/1572
Abstract: A multilayer wiring board includes a first metal foil wiring layer that has at least two or more layers of metal foil wiring lines and is arranged on a mounting surface side for mounting a surface mount type component, a wire wiring layer that is arranged on an opposite side of the mounting surface, and in which an insulation coating wire is wired, and a first interlayer conduction hole that has a conduction part which electrically connects the metal foil wiring line positioned on a surface of the first metal foil wiring layer to at least one of the metal foil wiring line in an inner layer of the first metal foil wiring layer and the insulation coating wire of the wire wiring layer. A hole diameter of the first interlayer conduction hole varies in a board thickness direction of the multilayer wiring board.
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Patent Agency Ranking
公开(公告)号：US09609749B2
公开(公告)日：2017-03-28
申请号：US14860718
申请日：2015-09-22
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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27.发明授权Printed wiring board having buildup layers and multilayer core substrate with double-sided board 有权具有堆积层的印刷电路板和具有双面板的多层芯基板公开(公告)号：US09578755B2
公开(公告)日：2017-02-21
申请号：US14255986
申请日：2014-04-18
Applicant: IBIDEN CO., LTD.
Inventor： Yoshio Mizutani , Hiroaki Watanabe
IPC: H05K3/46 , H05K3/42 , H01L23/498
CPC classification number: H05K3/462 , H01L23/49827 , H01L2924/0002 , H05K3/429 , H05K3/4602 , H05K2201/09509 , H05K2201/0959 , H05K2203/1476 , Y10T29/49165 , H01L2924/00
Abstract: A printed wiring board includes: a multilayer core substrate including first and second insulation layers and a double-sided board between the first and second insulation layers. The core substrate has a cylindrical through-hole structure including a cylindrical conductor through the insulation layers and the board, a resin filler filling inside the cylindrical conductor and covering circuits covering the filler at the ends of the cylindrical conductor, respectively. The core substrate includes a conductive layer including a through-hole land around end of the structure such that the land is directly connected to the cylindrical conductor, the land includes a first electroless film, a first electrolytic film, a second electroless film and a second electrolytic film, and the cylindrical conductor includes the second electroless and electrolytic films such that the second electroless film is in contact with the side walls of the first electroless and electrolytic films.
Abstract translation: 印刷电路板包括：包括第一绝缘层和第二绝缘层的多层芯基板和在第一绝缘层和第二绝缘层之间的双面板。 核心基板具有圆柱形通孔结构，其包括穿过绝缘层和板的圆柱形导体，填充在圆柱形导体内部的树脂填料和覆盖圆柱形导体端部的填料的覆盖电路。 核心基板包括导电层，该导电层包括在结构的端部周围的通孔焊盘，使得焊盘直接连接到圆柱形导体，焊盘包括第一化学镀膜，第一电解膜，第二无电镀膜和第二 所述圆筒形导体包括所述第二无电电解膜和所述电解质膜，使得所述第二无电解膜与所述第一无电解电解质膜和所述电解质膜的侧壁接触。
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公开(公告)号：US20170006713A1
公开(公告)日：2017-01-05
申请号：US14846991
申请日：2015-09-07
Applicant: Subtron Technology Co., Ltd.
Inventor： Chih-Hong Chuang , Chien-Hung Wu
CPC classification number: H05K1/09 , H01L21/4857 , H01L21/6835 , H01L23/49822 , H01L2221/68345 , H01L2221/68381 , H05K1/0298 , H05K1/115 , H05K3/0026 , H05K3/0047 , H05K3/007 , H05K3/18 , H05K3/205 , H05K3/4038 , H05K3/421 , H05K3/4638 , H05K3/4644 , H05K3/4682 , H05K2201/09509 , H05K2203/03
Abstract: A method of manufacturing a package substrate is provided. A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating copper layer formed thereon are provided and laminated, so that the first and the second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.
Abstract translation: 提供一种制造封装基板的方法。 提供了形成在其上的第一铜层和第一电镀铜层，形成在其上的第一电介质层，第二铜层和第二电镀铜层，形成在其上的第二电介质层，第三铜层和第三电镀铜层 并且层叠，使得第一和第二电介质层封装第二铜层和第二电镀铜层的边缘以形成临时载体。 在临时载体的两个相对的表面上形成两个电路结构。 切割临时载体和电路结构以暴露第二铜层和第二镀铜层的边缘，并沿着第二铜层和第二镀铜层的暴露边缘分离以形成独立于每个的两个封装衬底 其他。
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公开(公告)号：US09538636B1
公开(公告)日：2017-01-03
申请号：US13803081
申请日：2013-03-14
Applicant: MACOM Technology Solutions Holdings, Inc.
Inventor： Christopher D. Weigand , Andrzej Rozbicki
CPC classification number: H05K1/181 , H01L23/13 , H01L23/14 , H01L23/49805 , H01L23/49822 , H05K1/0201 , H05K1/0251 , H05K1/0306 , H05K1/115 , H05K1/14 , H05K1/141 , H05K1/18 , H05K3/0097 , H05K3/429 , H05K2201/041 , H05K2201/066 , H05K2201/09181 , H05K2201/09509 , H05K2201/09854 , H05K2201/10719
Abstract: An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.
Abstract translation: 公开了一种具有多个绝缘层，多个导电层和电镀层的装置。 导电层可以被绝缘层分离。 第一导电层中的第一图案通常延伸到边缘星座。 在第二导电层中的第二图案也可以延伸到边缘星座。 电镀可以设置在边缘地毯中并且将第一图案连接到第二图案。 地板中的电镀最多可以在导电层的子集之间延伸。
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公开(公告)号：US09510464B2
公开(公告)日：2016-11-29
申请号：US13590815
申请日：2012-08-21
Applicant: Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
Inventor： Tzyy-Jang Tseng , Shu-Sheng Chiang , Tsung-Yuan Chen
CPC classification number: H05K3/465 , C23C18/1612 , C23C18/1651 , C23C18/1653 , C23C18/1689 , H05K1/0265 , H05K3/0032 , H05K3/0035 , H05K3/045 , H05K3/107 , H05K2201/0391 , H05K2201/09509 , Y10T29/49155 , Y10T29/49165
Abstract: A manufacturing method of a circuit board is provided. A circuit substrate having a first surface and at least a first circuit is provided. A dielectric layer having a second surface and covering the first surface and the first circuit is formed on the circuit substrate. The dielectric layer is irradiated by a laser beam to form a first intaglio pattern, a second intaglio pattern and at least a blind via. A first conductive layer is formed in the first intaglio pattern, the second intaglio pattern and the blind via. A barrier layer and a second conductive layer are formed in the second intaglio pattern and the blind via. Parts of the second conductive layer, parts of the barrier layer and parts of the first conductive layer are removed until the second surface of the dielectric layer is exposed, so as to form a patterned circuit structure.
Abstract translation: 提供电路板的制造方法。 提供具有第一表面和至少第一电路的电路基板。 具有第二表面并覆盖第一表面的电介质层和第一电路形成在电路基板上。 电介质层被激光束照射以形成第一凹版图案，第二凹版图案和至少一个盲孔。 在第一凹版图案，第二凹版图案和盲孔中形成第一导电层。 在第二凹版图案和盲孔中形成阻挡层和第二导电层。 去除第二导电层的一部分，阻挡层的一部分和第一导电层的部分直到电介质层的第二表面露出，以形成图案化的电路结构。
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