公开(公告)号：US08354597B2

公开(公告)日：2013-01-15

申请号：US12216511

申请日：2008-07-07

Applicant: Takahiko Yokai ,  Toshiki Naito

Inventor： Takahiko Yokai ,  Toshiki Naito

IPC: H05K1/03 ,  G11B5/48 ,  H05K1/00

CPC classification number: H05K1/05 ,  H05K1/056 ,  H05K3/44 ,  H05K2201/09745 ,  H05K2201/10416 ,  H05K2203/0323 ,  H05K2203/0369 ,  H05K2203/0723 ,  Y10T29/49124

Abstract: A wired circuit board includes a metal supporting board having at least one depressed portion, a conductive portion embedded in the at least one depressed portion and formed of a material having a higher conductivity than that of the metal supporting board, an insulating layer formed on the metal supporting board so as to cover the conductive portion, and a plurality of wires formed on the insulating layer in mutually spaced-apart relation so as to oppose to the conductive portion.

Abstract translation: 布线电路板包括具有至少一个凹陷部分的金属支撑板，嵌入至少一个凹陷部分中的导电部分并且由具有比金属支撑板的导电性更高的导电性的材料形成，绝缘层形成在 金属支撑板以覆盖导电部分，并且以相互间隔的关系形成在绝缘层上以与导电部分相对的多个导线。

公开(公告)号：US08330258B2

公开(公告)日：2012-12-11

申请号：US10746745

申请日：2003-12-24

Applicant: Anthony M. Chiu ,  Tong Yan Tee

Inventor： Anthony M. Chiu ,  Tong Yan Tee

IPC: H01L23/02

CPC classification number: H01L21/4821 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/49582 ,  H01L2224/32245 ,  H01L2924/00014 ,  H05K3/341 ,  H05K3/3442 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10727 ,  H05K2201/10969 ,  Y02P70/613 ,  H01L2224/45099

Abstract: A system and method is disclosed for improving solder joint reliability in an integrated circuit package. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package.

Abstract translation: 公开了一种用于提高集成电路封装中的焊点可靠性的系统和方法。 四边形，平坦的，非引线的集成电路封装的每个端子形成有在端子的底表面中限定焊料槽的部分。 集成电路封装的管芯焊盘的外表面也形成有在管芯焊盘的外围限定多个焊料槽的部分。 当焊料施加到管芯焊盘和端子时，填充焊料槽的焊料增加了集成电路封装的焊点可靠性。

公开(公告)号：US08316540B2

公开(公告)日：2012-11-27

申请号：US12212927

申请日：2008-09-18

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and mounting at least one interposer on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. At least one sidewall of the interposer is slitted to facilitate the venting of gases and pressure therethrough. The method includes arranging a plurality of electrically-conductive elements about the surface of the at least one hemi-toroidal interposer and extending them radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及在所述载体平面的第一表面上安装至少一个插入件的方法。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 插入器的至少一个侧壁被切割以便于气体的排出和通过其中的压力。 该方法包括围绕至少一个半环形插入器的表面布置多个导电元件，并从其最上端向内和向下自由地延伸，以与位于该至少一个半环形插入器的相对侧上的至少一个部件电接触 电绝缘载体平面。

公开(公告)号：US20120235172A1

公开(公告)日：2012-09-20

申请号：US13326623

申请日：2011-12-15

Applicant: KURT DOUGLAS ROBERTS

Inventor： KURT DOUGLAS ROBERTS

IPC: H01L33/64

CPC classification number: F21K9/23 ,  F21K9/27 ,  F21S4/24 ,  F21V29/70 ,  F21V29/74 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/642 ,  H01L2924/0002 ,  H05K1/0278 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/09745 ,  H05K2201/10106 ,  H01L2924/00

Abstract: A flexible layered structure is disclosed having a flexible top conductive layer, a flexible bottom heat sink layer and a flexible dielectric middle layer. The combination has a longitudinal axis and a plurality of defined positions spaced along the longitudinal axis. The defined positions can be used for aligning a circuit and/or for the placement of LED lights. The flexible layered structure can be easily bent to form a LED substrate for shining light in more than one direction while efficiently removing heat arising from the LEDs.

Abstract translation: 公开了一种柔性分层结构，其具有柔性顶部导电层，柔性底部散热层和柔性电介质中间层。 该组合具有纵向轴线和沿着纵向轴线间隔开的多个限定位置。 定义的位置可用于对齐电路和/或放置LED灯。 柔性层状结构可以容易地弯曲以形成用于在多于一个方向上发光的LED基板，同时有效地去除由LED产生的热量。

公开(公告)号：US08242587B2

公开(公告)日：2012-08-14

申请号：US12177210

申请日：2008-07-22

Applicant: Hiromichi Ebine ,  Katsuhiko Kikuchi ,  Satoshi Shimada ,  Masahide Hayashi

Inventor： Hiromichi Ebine ,  Katsuhiko Kikuchi ,  Satoshi Shimada ,  Masahide Hayashi

IPC: H01L23/31

CPC classification number: H05K3/3442 ,  H01L2924/0002 ,  H05K3/202 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/09745 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic device requires an electronic component to be mounted for the purpose of static shielding. The mounting of such an electronic component raises a problem of avoiding thermal stresses and cracks generated due to the difference between the coefficients of linear expansion of component materials. A positioning recess, a joining-substance thickness ensuring recess, a joining-substance thickness ensuring projection, etc. are formed in a combined manner in an electronic component mount portion of each of leads, whereby spreading of cracks generated in the joining substance can be suppressed and reliability can be improved. Filling a sealing material so as to seal and restrain the electronic component mounted in the electronic component mount portion without leaving voids contributes to further suppressing spreading of cracks generated in the joining substance and ensuring more improved reliability of the joining substance.

Abstract translation: 电子设备需要为了静电屏蔽而安装电子部件。 这种电子部件的安装提出了避免由于部件材料的线性膨胀系数之间的差异而产生的热应力和裂纹的问题。 在各引线的电子部件安装部中，以组合的方式形成定位凹部，接合物质厚度确保凹部，接合物质厚度确保凹部等，由此在接合物质中产生的裂纹的扩散可以 可以提高抑制和可靠性。 填充密封材料以密封和限制安装在电子部件安装部分中的电子部件而不留空隙有助于进一步抑制在接合物质中产生的裂纹的扩散，并确保接合物质的可靠性更好。

公开(公告)号：US08236666B2

公开(公告)日：2012-08-07

申请号：US12664751

申请日：2007-12-05

Applicant: Seiki Hiramatsu ,  Kei Yamamoto ,  Atsuko Fujino ,  Takashi Nishimura ,  Kenji Mimura ,  Hideki Takigawa ,  Hiroki Shiota ,  Nobutake Taniguchi ,  Hiroshi Yoshida

Inventor： Seiki Hiramatsu ,  Kei Yamamoto ,  Atsuko Fujino ,  Takashi Nishimura ,  Kenji Mimura ,  Hideki Takigawa ,  Hiroki Shiota ,  Nobutake Taniguchi ,  Hiroshi Yoshida

IPC: H01L21/00 ,  H01L21/46 ,  H01L21/30

CPC classification number: H01L23/3737 ,  H01L23/16 ,  H01L23/3121 ,  H01L23/3735 ,  H01L23/5386 ,  H01L23/562 ,  H01L2224/48091 ,  H01L2924/09701 ,  H01L2924/19107 ,  H05K1/056 ,  H05K3/041 ,  H05K3/202 ,  H05K3/44 ,  H05K2201/0209 ,  H05K2201/09745 ,  H05K2201/09881 ,  H01L2924/00014

Abstract: Provided is a semiconductor device including: a base plate; a thermally conductive resin layer formed on an upper surface of the base plate; an integrated layer which is formed on an upper surface of the thermally conductive resin layer, and includes an electrode and an insulating resin layer covering all side surfaces of the electrode; and a semiconductor element formed on an upper surface of the electrode, in which the integrated layer is thermocompression bonded to the base plate through the thermally conductive resin layer. This semiconductor device excels in insulating properties and reliability.

Abstract translation: 提供一种半导体器件，包括：基板; 形成在所述基板的上表面上的导热树脂层; 形成在导热性树脂层的上表面的整体层，具有覆盖电极的所有侧面的电极和绝缘性树脂层; 以及形成在所述电极的上表面上的半导体元件，其中所述一体层通过所述导热树脂层热压接合到所述基板。 该半导体器件的绝缘性和可靠性优异。

公开(公告)号：US08227702B2

公开(公告)日：2012-07-24

申请号：US12385134

申请日：2009-03-31

Applicant: Hatsuo Ikeda ,  Koji Ichikawa

Inventor： Hatsuo Ikeda ,  Koji Ichikawa

IPC: H05K1/09

CPC classification number: H05K1/113 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K3/246 ,  H05K3/4061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0347 ,  H05K2201/09745 ,  H01L2224/05599

Abstract: A multilayer ceramic substrate in which an active element and a passive element are surface-equipped over the outermost surface on one side is provided. The multilayer ceramic substrate comprises a plurality of laminated ceramic substrate layers, a surface layer terminal electrode provided in a via hole of an outermost ceramic substrate layer on at least one side and having a surface layer via electrode and a metal plating layer deposited over an end surface of the surface layer via electrode, and a via conductor which connects the surface layer terminal electrode and circuit patterns over the ceramic substrate layer at the inside, wherein a via hole size of a surface layer terminal electrode for connection of the active element is smaller than a via hole size of a surface layer terminal electrode for connection of the passive element.

Abstract translation: 提供一种多层陶瓷基板，其中在一侧的最外表面上表面配置有源元件和无源元件。 多层陶瓷基板包括多个层叠陶瓷基板层，表面层端子电极，设置在至少一侧的最外侧陶瓷基板层的通路孔中，具有表面层通孔电极和沉积在端部的金属镀层 表面层通孔电极的表面，以及将内表面层端子电极和电路图案连接在陶瓷基板层上的通孔导体，其中用于连接有源元件的表面层端子电极的通孔尺寸较小 比用于连接无源元件的表面层端子电极的通孔尺寸。

公开(公告)号：US08227175B2

公开(公告)日：2012-07-24

申请号：US12467291

申请日：2009-05-17

Applicant: Chung-Jen Tsai ,  Yu-Cheng Huang ,  Hung-Yi Chang ,  Cheng-Hsien Lin

Inventor： Chung-Jen Tsai ,  Yu-Cheng Huang ,  Hung-Yi Chang ,  Cheng-Hsien Lin

IPC: H05K3/00

CPC classification number: H05K3/4644 ,  H05K3/0094 ,  H05K3/421 ,  H05K2201/09563 ,  H05K2201/09745 ,  H05K2203/025 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method for smoothing a printed circuit board (PCB), comprising: providing a PCB having a first smooth outer surface and an opposite second outer surface, the second outer surface including a smooth region and a plurality of dimples; applying a liquid photoresist layer onto the second outer surface of the PCB to fill the dimples; solidifying the liquid photoresist in the dimples to obtain a solidified photoresist layer; polishing the solidified photoresist layer until a surface thereof being coplanar with the smooth region; and polishing the entire second outer surface until the solidified photoresist layer is removed, thereby obtaining a plain outer surface parallel to the first smooth outer surface.

Abstract translation: 一种用于平滑印刷电路板（PCB）的方法，包括：提供具有第一光滑外表面和相对的第二外表面的PCB，所述第二外表面包括平滑区域和多个凹坑; 将液体光致抗蚀剂层施加到PCB的第二外表面上以填充凹坑; 在凹坑中固化液体光致抗蚀剂以获得固化的光致抗蚀剂层; 抛光固化的光致抗蚀剂层，直到其表面与光滑区域共面; 并且抛光整个第二外表面直到去除固化的光致抗蚀剂层，从而获得平行于第一光滑外表面的平原外表面。

公开(公告)号：US20120127666A1

公开(公告)日：2012-05-24

申请号：US13007545

申请日：2011-01-14

Applicant: Ji Hyun PARK ,  Seog Moon CHOI ,  Young Ki LEE

Inventor： Ji Hyun PARK ,  Seog Moon CHOI ,  Young Ki LEE

IPC: H05K7/20 ,  H05K1/00 ,  H05K3/00 ,  C23C28/00 ,  C25D7/00

CPC classification number: H05K1/053 ,  H05K2201/09745

Abstract: Disclosed herein are a heat-radiating substrate and a method of manufacturing the same. The heat-radiating substrate includes: a base substrate with a heat sink, having a groove; an insulating layer formed on the base substrate by performing anodization thereon; and a circuit layer formed on the insulating layer, whereby the heat-radiating substrate with the heat-sink, made of metal material, is manufactured, thereby making it possible to protect devices weak against heat and thus solve the problem in view of reduced life span and degraded reliability.

Abstract translation: 这里公开了散热基板及其制造方法。 散热基板包括：具有散热器的基底，具有凹槽; 绝缘层，其通过在其上进行阳极氧化而形成在所述基底基板上; 以及形成在绝缘层上的电路层，由此制造具有由金属材料制成的散热器的散热基板，从而可以保护弱热的器件，从而解决了降低寿命的问题 跨度和可靠性降低。

公开(公告)号：US08153186B2

公开(公告)日：2012-04-10

申请号：US12541407

申请日：2009-08-14

Applicant: Masayuki Nagamatsu ,  Ryosuke Usui

Inventor： Masayuki Nagamatsu ,  Ryosuke Usui

IPC: H05K3/00

CPC classification number: H05K1/111 ,  H01L23/295 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/383 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/0542 ,  Y02P70/611 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0401

Abstract: An advantage of the present invention is to suppress moisture infiltrating from a pad electrode portion from spreading over the surface of a wiring pattern and improve the reliability of a packaging board. The wiring pattern of the packaging board is formed on an insulating substrate and includes a wiring region, an electrode region (pad electrode) connected with a semiconductor device, and a boundary region provided between the wiring region and the electrode region. A gold plating layer is provided on the surface of the electrode region of the wiring pattern. The top surface of the boundary region of the wiring pattern is so formed as to be dented from the top surface of the wiring region of the wiring pattern, and there is provided a stepped portion in the boundary region. A solder resist is formed in such a manner as to cover part of the gold plating layer and the wiring pattern corresponding to the boundary region and the wiring region, and the solder resist has a predetermined opening through which to connect to the semiconductor device. A conductive member is connected to the gold plating layer in the electrode region, and a molded resin layer seals the entire semiconductor module.

Abstract translation: 本发明的优点是抑制从焊盘电极部分渗透的湿气在布线图案的表面上扩散，并提高包装板的可靠性。 包装板的布线图案形成在绝缘基板上，并且包括布线区域，与半导体器件连接的电极区域（焊盘电极）以及设置在布线区域和电极区域之间的边界区域。 在布线图案的电极区域的表面上设置镀金层。 布线图案的边界区域的顶表面被形成为从布线图案的布线区域的顶表面凹陷，并且在边界区域中设置有台阶部分。 形成阻焊层，以覆盖与边界区域和布线区域相对应的金镀层和布线图案的一部分，阻焊剂具有与半导体器件连接的预定开口。 导电构件连接到电极区域中的镀金层，并且模制树脂层密封整个半导体模块。