公开(公告)号：US20110193229A1

公开(公告)日：2011-08-11

申请号：US13013290

申请日：2011-01-25

Applicant: Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

Inventor： Keum-Hee Ma ,  Woo-Dong Lee ,  Min-Seung Yoon ,  Ju-il Choi ,  Sang-Sick Park ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L23/481 ,  H01L23/49816 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555

Abstract: A semiconductor device having semiconductor chips of different thicknesses is provided. The semiconductor device may include a first semiconductor chip, a sub-board on a first side of the first semiconductor chip, at least one second semiconductor chip on a second side of the first semiconductor chip, at least one external contact terminal on the at least one second semiconductor chip. In example embodiments the at least one second semiconductor chip may include a plurality of through silicon vias and the at least one external contact terminal may be in electrical contact with the first semiconductor chip and the at least one second semiconductor chip via the plurality of through silicon vias. In example embodiments, the at least one second semiconductor chip may be thinner than the first semiconductor chip.

Abstract translation: 提供具有不同厚度的半导体芯片的半导体器件。 半导体器件可以包括第一半导体芯片，在第一半导体芯片的第一侧上的子板，在第一半导体芯片的第二侧上的至少一个第二半导体芯片，至少一个外部接触端子 一秒钟的半导体芯片。 在示例实施例中，所述至少一个第二半导体芯片可以包括多个通孔硅通孔，并且所述至少一个外部接触端子可以经由多个通孔与第一半导体芯片和至少一个第二半导体芯片电接触 通孔 在示例实施例中，至少一个第二半导体芯片可以比第一半导体芯片更薄。

公开(公告)号：US20110147946A1

公开(公告)日：2011-06-23

申请号：US13027594

申请日：2011-02-15

Applicant: In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

Inventor： In-Young Lee ,  Ho-Jin Lee ,  Hyun-Soo Chung ,  Ju-Il Choi ,  Son-Kwan Hwang

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01055 ,  H01L2924/0106 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2224/05552

Abstract: A method of manufacturing a semiconductor device includes forming an integrated circuit region on a semiconductor wafer. A first metal layer pattern is formed over the integrated circuit region. A via hole is formed to extend through the first metal layer pattern and the integrated circuit region. A final metal layer pattern is formed over the first metal layer pattern and within the via hole. A plug is formed within the via hole. Thereafter, a passivation layer is formed to overlie the final metal layer pattern.

Abstract translation: 一种制造半导体器件的方法包括在半导体晶片上形成集成电路区域。 在集成电路区域上形成第一金属层图案。 通孔形成为延伸穿过第一金属层图案和集成电路区域。 最终的金属层图案形成在第一金属层图案之上并且在通孔内。 在通孔内形成插头。 此后，形成钝化层以覆盖最终金属层图案。

公开(公告)号：US20110108415A1

公开(公告)日：2011-05-12

申请号：US12938797

申请日：2010-11-03

Applicant: UIHYOUNG LEE ,  Namseog Kim ,  WoonHo Seo ,  Min-Suk Han ,  YoungHyun Ju ,  Ju-il Choi

Inventor： UIHYOUNG LEE ,  Namseog Kim ,  WoonHo Seo ,  Min-Suk Han ,  YoungHyun Ju ,  Ju-il Choi

IPC: C25D17/00

CPC classification number: C25D17/005 ,  C25D17/001 ,  C25D17/008 ,  C25D17/02 ,  C25D21/10

Abstract: An apparatus for electroplating a substrate includes a substrate supporting member that supports the substrate such that a plating surface of the substrate faces upwardly, an anode electrode disposed at an upper part of the substrate supporting member, a power source for applying a voltage to the anode electrode and the substrate, and a plating solution supply member for supplying a plating solution onto the substrate.

Abstract translation: 一种用于电镀衬底的设备包括：衬底支撑构件，其支撑衬底，使得衬底的电镀表面朝上，设置在衬底支撑构件的上部的阳极，用于向阳极施加电压的电源 电极和基板，以及用于将电镀液供给到基板上的电镀液供给部件。

公开(公告)号：US20110086486A1

公开(公告)日：2011-04-14

申请号：US12969977

申请日：2010-12-16

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20100285635A1

公开(公告)日：2010-11-11

申请号：US12840656

申请日：2010-07-21

Applicant: Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

Inventor： Cha-Jea Jo ,  Myung-Kee Chung ,  Nam-Seog Kim ,  In-Young Lee ,  Seok-Ho Kim ,  Ho-Jin Lee ,  Ju-Il Choi ,  Chang-Woo Shin

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2224/05599

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract translation: 芯片堆叠封装包括基板，多个芯片，多个粘合剂层和插头。 基板具有形成在布线图案上的布线图案和种子层。 每个芯片具有电极焊盘和穿过电极焊盘的第一通孔。 芯片被堆叠，使得第一通孔在衬底的籽晶层上排列。 粘合层介于基片和芯片之一之间以及芯片之间。 每个粘合层具有连接到第一通孔的第二通孔。 插头填充第一通孔和第二通孔，并将电极焊盘电连接到衬底的布线图案。 第二通孔中的插塞的横截面面积可以大于第一通孔中的插头的横截面面积。

公开(公告)号：US20070069320A1

公开(公告)日：2007-03-29

申请号：US11486041

申请日：2006-07-14

Applicant: In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

Inventor： In-Young Lee ,  Sung-Min Sim ,  Dong-Hyeon Jang ,  Hyun-Soo Chung ,  Jae-Sik Chung ,  Seung-Kwan Ryu ,  Myeong-Soon Park ,  Jong-Kook Yoon ,  Ju-Il Choi

IPC: H01L31/00

CPC classification number: H01L24/12 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/114 ,  H01L2224/1148 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/274 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A wiring structure may include a pad, a conductive pattern and an insulating photoresist structure. The pad may be provided on a body and electrically connected to a circuit unit of the body. The conductive pattern may be provided on the body and may be electrically connected to the pad. The insulating photoresist structure may be provided on a surface of the conductive pattern. The insulating photoresist structure may have a contact hole through which the conductive pattern may be partially exposed. The insulating photoresist structure may be fabricated by providing a photosensitive photoresist film on the conductive layer, and patterning the photosensitive photoresist film by two photo processes.

Abstract translation: 布线结构可以包括垫，导电图案和绝缘光致抗蚀剂结构。 垫可以设置在主体上并电连接到主体的电路单元。 导电图案可以设置在主体上并且可以电连接到垫。 绝缘光致抗蚀剂结构可以设置在导电图案的表面上。 绝缘光致抗蚀剂结构可以具有接触孔，导电图案可以通过该接触孔部分地暴露。 绝缘光致抗蚀剂结构可以通过在导电层上提供感光性光致抗蚀剂膜，并通过两个照相工艺对感光性光刻胶膜进行图案化来制造。

公开(公告)号：US09735090B2

公开(公告)日：2017-08-15

申请号：US14873453

申请日：2015-10-02

Applicant: Ju-il Choi ,  Atsushi Fujisaki ,  Byung-Iyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

Inventor： Ju-il Choi ,  Atsushi Fujisaki ,  Byung-Iyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13552 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/01074

Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

公开(公告)号：US08778776B2

公开(公告)日：2014-07-15

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US08629059B2

公开(公告)日：2014-01-14

申请号：US12969977

申请日：2010-12-16

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US08575760B2

公开(公告)日：2013-11-05

申请号：US13303255

申请日：2011-11-23

Applicant: Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

Inventor： Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

IPC: H01L23/498

CPC classification number: H01L29/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05571 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Abstract translation: 半导体器件包括具有第一表面和相对的第二表面的衬底。 电极在衬底内朝向第一表面延伸并且具有从第一表面延伸的突出部分。 支撑部分从基板的第一表面延伸到突出部分的侧壁并支撑突出部分。