公开(公告)号：US08575760B2

公开(公告)日：2013-11-05

申请号：US13303255

申请日：2011-11-23

Applicant: Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

Inventor： Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

IPC: H01L23/498

CPC classification number: H01L29/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05571 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Abstract translation: 半导体器件包括具有第一表面和相对的第二表面的衬底。 电极在衬底内朝向第一表面延伸并且具有从第一表面延伸的突出部分。 支撑部分从基板的第一表面延伸到突出部分的侧壁并支撑突出部分。

公开(公告)号：US20120133041A1

公开(公告)日：2012-05-31

申请号：US13303255

申请日：2011-11-23

Applicant: Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

Inventor： Jae-hyun Phee ,  Uihyouong Lee ,  Ju-il Choi ,  Jung-Hwan Kim

IPC: H01L23/498

CPC classification number: H01L29/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/05571 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13076 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Some embodiments provide a semiconductor device including a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion that supports the protruding portion. Methods of fabricating the same are also provided.

Abstract translation: 一些实施例提供包括具有第一表面和相对的第二表面的基板的半导体器件。 电极在衬底内朝向第一表面延伸并且具有从第一表面延伸的突出部分。 支撑部分从基板的第一表面延伸到支撑突出部分的突出部分的侧壁。 还提供了制造方法。

公开(公告)号：US08778776B2

公开(公告)日：2014-07-15

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US20120083097A1

公开(公告)日：2012-04-05

申请号：US13187760

申请日：2011-07-21

Applicant: Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

Inventor： Ju-il Choi ,  Kyu-Ha Lee ,  Jae-Hyun Phee ,  Jung-Hwan Kim ,  Tae Hong Min

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/486 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2224/02372 ,  H01L2224/1146 ,  H01L2224/116 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81903 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2224/81 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: Provided is a method of forming a semiconductor package including providing a substrate having a first side and an opposite second side and providing a wafer having a plurality of semiconductor chips, each of the semiconductor chips having a conductive pad, wherein at least one of the substrate and the wafer includes a seed pattern. The first side of the substrate is bonded to the wafer with the conductive pad positioned adjacent to the first side of the substrate and the seed pattern positioned between the conductive pad and the first side of the substrate. A through hole is then formed penetrating the substrate from the second side of the substrate to expose the seed pattern. A through electrode is formed in the through hole using the seed pattern as a seed. Corresponding devices are also provided.

Abstract translation: 提供一种形成半导体封装的方法，包括提供具有第一侧和相对的第二侧的衬底，并提供具有多个半导体芯片的晶片，每个半导体芯片具有导电焊盘，其中至少一个衬底 并且晶片包括种子图案。 衬底的第一面被接合到晶片，其中导电焊盘定位成与衬底的第一侧相邻，并且种子图案位于导电焊盘和衬底的第一侧之间。 然后从衬底的第二侧穿透衬底以形成通孔以暴露种子图案。 使用种子图案作为种子在通孔中形成贯通电极。 还提供了相应的设备。

公开(公告)号：US20120199981A1

公开(公告)日：2012-08-09

申请号：US13364678

申请日：2012-02-02

Applicant: Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

Inventor： Se-young Jeong ,  Ho-geon Song ,  Ju-il Choi ,  Jae-hyun Phee

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/10135 ,  H01L2224/11015 ,  H01L2224/11464 ,  H01L2224/11622 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13171 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/27436 ,  H01L2224/27622 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/81862 ,  H01L2224/81986 ,  H01L2224/83862 ,  H01L2224/92143 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06575 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/3511 ,  H01L2924/3651 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a first device including a first substrate and a first external connection terminal for connecting outside the first device; a second device stacked on the first device, the second device including a second substrate and a second external connection terminal for connecting outside the second device; an adhesive pattern disposed between the first device and second device, the adhesive pattern disposed in locations other than locations where the first external connection terminal and second external connection terminal are disposed, and the adhesive pattern causing the first device and second device, when stacked, to be spaced apart by a predetermined distance; and a plated layer disposed between and electrically and physically connecting the first external connection terminal and the second external connection terminal.

Abstract translation: 半导体器件包括：第一器件，包括第一衬底和用于连接第一器件外部的第一外部连接端子; 堆叠在第一装置上的第二装置，第二装置包括第二基板和用于连接第二装置外部的第二外部连接端子; 布置在第一装置和第二装置之间的粘合剂图案，布置在除了设置第一外部连接端子和第二外部连接端子的位置以外的位置的粘合剂图案以及当堆叠时引起第一装置和第二装置的粘合剂图案， 间隔开预定距离; 以及设置在电气和物理上连接第一外部连接端子和第二外部连接端子之间的镀层。

公开(公告)号：US20110226626A1

公开(公告)日：2011-09-22

申请号：US13039822

申请日：2011-03-03

Applicant: Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

Inventor： Ju-il Choi ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park

IPC: C25D5/48 ,  H01L21/306

CPC classification number: H01L21/6723 ,  C25D7/123 ,  C25D17/001 ,  C25D17/06 ,  H01L21/67028 ,  H01L21/6708 ,  H01L21/6719 ,  H01L21/68728 ,  H01L21/68785

Abstract: A substrate treating device may include a plating treatment portion configured to perform a plating process of a substrate, a wet treatment portion configured to perform a wet treating process of the substrate, the wet treatment portion being under the plating treatment portion, and a substrate support portion configured to support the substrate so that a plating surface of the substrate faces upward, the substrate support portion being further configured to move the substrate between the plating treatment portion and the wet treatment portion.

Abstract translation: 基板处理装置可以包括：电镀处理部，被配置为进行基板的电镀处理;湿处理部，被配置为进行基板的湿式处理;湿处理部位于电镀处理部下;以及基板支撑 被配置为支撑所述基板的部分，使得所述基板的电镀表面面向上，所述基板支撑部分还被配置为在所述电镀处理部分和所述湿处理部分之间移动所述基板。

公开(公告)号：US08564102B2

公开(公告)日：2013-10-22

申请号：US13108231

申请日：2011-05-16

Applicant: Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

Inventor： Ju-il Choi ,  Jae-hyun Phee ,  Kyu-ha Lee ,  Ho-jin Lee ,  Son-kwan Hwang

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76879 ,  H01L21/76844 ,  H01L21/76873 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05009 ,  H01L2224/06181

Abstract: A semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes an interlayer insulation layer pattern, a metal wire pattern exposed by a passage formed by a via hole formed in the interlayer insulation layer pattern to input and output an electrical signal, and a plated layer pattern directly contacting the metal wire pattern and filling the via hole. The method includes forming an interlayer insulation layer having a metal wire pattern to input and output an electrical signal formed therein, forming a via hole to define a passage that extends through the interlayer insulation layer until at least a part of the metal wire pattern is exposed, and forming a plated layer pattern to fill the via hole and to directly contact the metal wire pattern by using the metal wire pattern exposed through the via hole as a seed metal layer.

Abstract translation: 半导体器件和半导体器件的制造方法。 半导体器件包括层间绝缘层图案，由形成在层间绝缘层图案中的通孔形成的通道暴露的金属线图案，以输入和输出电信号，以及直接接触金属线图案的镀层图案和 填充通孔。 该方法包括形成具有金属线图案的层间绝缘层，以输入和输出其中形成的电信号，形成通孔以限定延伸穿过层间绝缘层的通道，直到金属线图案的至少一部分露出 并且形成镀层图案以填充通孔并且通过使用通过通孔露出的金属线图案作为种子金属层直接接触金属线图案。

公开(公告)号：US07875552B2

公开(公告)日：2011-01-25

申请号：US12476793

申请日：2009-06-02

Applicant: Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

Inventor： Ho-Jin Lee ,  Kang-Wook Lee ,  Myeong-Soon Park ,  Ju-il Choi ,  Son-Kwan Hwang

IPC: H01L23/48

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的第一表面上形成层间电介质层，然后形成延伸穿过层间电介质层并进入半导体衬底的互连孔。 第一侧壁间隔层形成在互连孔的侧壁上。 在互连孔的底部的半导体衬底被各向同性蚀刻以在半导体衬底中限定底切凹部。 该蚀刻步骤使用第一侧壁间隔层作为蚀刻掩模进行。 然后用通孔电极填充互连孔和未切割凹部。 去除半导体衬底的第二表面足够的持续时间以露出包含通孔电极的未切割凹部。

公开(公告)号：US20160099201A1

公开(公告)日：2016-04-07

申请号：US14873453

申请日：2015-10-02

Applicant: Ju-il Choi ,  Atsushi Fujisaki ,  Byung-lyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

Inventor： Ju-il Choi ,  Atsushi Fujisaki ,  Byung-lyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

IPC: H01L23/498 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13552 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/01074

Abstract: An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

Abstract translation: 集成电路器件包括半导体结构，穿透半导体结构的穿透硅通孔（TSV）结构和连接到TSV结构的连接端子。 金属覆盖层包括覆盖连接端子的底表面的平坦封盖部分和与扁平封盖部分整体连接并部分覆盖连接端子的侧壁的楔形封盖部分。 金属覆盖层可以通过电镀工艺形成，其中连接端子与金属冲击电镀溶液接触，同时施加脉冲型电流。

公开(公告)号：US07767576B2

公开(公告)日：2010-08-03

申请号：US11556931

申请日：2006-11-06

Applicant: Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

Inventor： Hyun-soo Chung ,  Seung-duk Baek ,  Ju-il Choi ,  Dong-ho Lee

IPC: H01L21/4763

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/12 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/02335 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/4813 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of forming a wire structure connecting to a bonding pad of a semiconductor chip includes depositing a passivation layer on an active surface of the semiconductor chip, depositing a seed metal layer on the bonding pad and the passivation layer, depositing a metal layer on the seed metal layer, etching selected portions of the seed metal layer, leaving unetched a first area, overlapping the bonding pad and a second area overlapping a connection pad, wherein the wire structure is formed by the metal layer being electrically connected to the bonding pad and the connection pad, but floating from the passivation layer, and depositing an insulting layer on the wire structure.

Abstract translation: 形成连接到半导体芯片的焊盘的导线结构的方法包括在半导体芯片的有源表面上沉积钝化层，在焊盘和钝化层上沉积种子金属层，在金属层上沉积金属层 种子金属层，蚀刻种子金属层的选定部分，留下未蚀刻的第一区域，与接合焊盘重叠，第二区域与连接焊盘重叠，其中线结构由金属层电连接到接合焊盘， 连接焊盘，但是从钝化层浮起，并且在导线结构上沉积绝缘层。