公开(公告)号：US07572726B2

公开(公告)日：2009-08-11

申请号：US11271760

申请日：2005-11-10

Applicant: Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

Inventor： Julie C. Biggs ,  Tien-Jen Cheng ,  David E. Eichstadt ,  Lisa A. Fanti ,  Jonathan H. Griffith ,  Randolph F. Knarr ,  Sarah H. Knickerbocker ,  Kevin S. Petrarca ,  Roger A. Quon ,  Wolfgang Sauter ,  Kamalesh K. Srivastava ,  Richard P. Volant

IPC: H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/85205 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.

Abstract translation: 一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。 在衬垫的暴露表面和开口表面上形成至少第一导电层。 在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。 在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。 本发明还包括所得到的结构。

公开(公告)号：US07566649B2

公开(公告)日：2009-07-28

申请号：US11858147

申请日：2007-09-20

Applicant: William E. Bernier ,  Tien-Jen Cheng ,  Marie S. Cole ,  David E. Eichstadt ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Lewis S. Goldmann ,  John U. Knickerbocker ,  Tasha E. Lopez ,  David J. Welsh

Inventor： William E. Bernier ,  Tien-Jen Cheng ,  Marie S. Cole ,  David E. Eichstadt ,  Mukta G. Farooq ,  John A. Fitzsimmons ,  Lewis S. Goldmann ,  John U. Knickerbocker ,  Tasha E. Lopez ,  David J. Welsh

IPC: H01L21/44 ,  H01L21/50 ,  H01L21/48 ,  H01L23/52 ,  H01L23/48 ,  H01L23/485 ,  H01L23/488

CPC classification number: H01L21/563 ,  H01L23/3171 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13566 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R43/0256 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/0401

Abstract: Disclosed is a method of forming an integrated circuit structure that forms lead-free connectors on a device, surrounds the lead-free connectors with a compressible film, connects the device to a carrier (the lead-free connectors electrically connect the device to the carrier), and fills the gaps between the carrier and the device with an insulating underfill.

Abstract translation: 公开了一种形成集成电路结构的方法，其在器件上形成无铅连接器，用可压缩膜围绕无铅连接器，将器件连接到载体（无铅连接器将器件电连接到载体上 ），并用绝缘底部填充物填充载体和装置之间的间隙。

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

Applicant: Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

Inventor： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

Abstract: A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

Abstract translation: 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US20050245070A1

公开(公告)日：2005-11-03

申请号：US10709321

申请日：2004-04-28

Applicant: Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

Inventor： Panayotis Andricacos ,  Tien-Jen Cheng ,  Emanuel Cooper ,  David Eichstadt ,  Jonathan Griffith ,  Randolph Knarr ,  Roger Quon ,  Erik Roggeman

IPC: H01L21/288 ,  H01L21/4763 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/2885 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/01028 ,  H01L2924/00014

Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.

Abstract translation: 公开了一种创建用于互连中的多层屏障的方法，用于互连的屏障和包括屏障的互连的方法。 该方法包括通过使用单个电镀化学品在器件端子的凹部中产生多层屏障，以增强由于铜的扩散而导致的排除和去层压的保护，无论是通过自扩散还是电迁移。 屏障包括至少第一层富镍材料和第二层富铜材料。 阻挡层可以为高级互补金属氧化物半导体（CMOS）设计使用更高的电流密度，并扩展电流CMOS设计的可靠性，无论焊料选择如何。 而且，该技术很容易适用于电镀互连如C4的制造方法。

公开(公告)号：US06924185B2

公开(公告)日：2005-08-02

申请号：US10680618

申请日：2003-10-07

Applicant: David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

Inventor： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC: H01L23/525 ,  H01L21/336

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

Abstract translation: 用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。 保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。 界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。 熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。 保险丝元件是电镀，无电镀，或是超薄保险丝。

公开(公告)号：US5728433A

公开(公告)日：1998-03-17

申请号：US808694

申请日：1997-02-28

Applicant: Tien-Jen Cheng ,  David B. Shields

Inventor： Tien-Jen Cheng ,  David B. Shields

IPC: C23C18/16 ,  B05D1/18

CPC classification number: C23C18/1617

Abstract: A method for replenishing an electroless gold plating bath in which metallic gold is dissolved into the bath.

Abstract translation: 一种用于补充其中金属金溶解到浴中的无电镀金浴的方法。

公开(公告)号：US20130095649A1

公开(公告)日：2013-04-18

申请号：US13274413

申请日：2011-10-17

Applicant: Tien-Jen Cheng ,  John Anthony Fitzsimmons ,  David E. Speed ,  Keith Kwong Hon Wong

Inventor： Tien-Jen Cheng ,  John Anthony Fitzsimmons ,  David E. Speed ,  Keith Kwong Hon Wong

IPC: H01L21/3205 ,  C25D17/00

CPC classification number: C23C18/1617 ,  C23C18/50 ,  C25D21/22 ,  H01L21/288 ,  H01L21/76849

Abstract: Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath.

Abstract translation: 通过诸如电镀的反应从化学浴中耗尽的离子通过选择性渗透膜的生产和移动而不断补充，同时从化学浴中分离潜在的污染物离子。

公开(公告)号：US08415252B2

公开(公告)日：2013-04-09

申请号：US12683857

申请日：2010-01-07

Applicant: Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

Inventor： Tien-Jen Cheng ,  Abhishek Dube ,  Zhengwen Li ,  Huilong Zhu

IPC: H01L21/44

CPC classification number: H01L21/76834 ,  H01L21/76826 ,  H01L21/76832 ,  H05K3/282 ,  H05K3/388 ,  H05K3/4682

Abstract: A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.

Abstract translation: 金属互连结构在含铜结构中的铜原子和自对准铜封装层之间提供高粘合强度，其仅选择性地沉积在暴露的铜表面上。 下层金属互连结构包括第一介电材料层和嵌入在下金属衬里中的含铜结构。 在形成含铜结构的平坦化工艺之后，将含铜结构体的露出表面形成Cu-S键的材料施加到含铜结构体的表面。 该材料仅选择性地沉积在暴露的Cu表面上，从而形成自对准的铜封装层，并且对下面的铜表面提供高粘附强度。 随后可以在铜封装层上形成电介质盖层和上层金属互连结构。

公开(公告)号：US07923836B2

公开(公告)日：2011-04-12

申请号：US11459119

申请日：2006-07-21

Applicant: Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

Inventor： Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

Abstract translation: 提供微电子元件及其制造方法。 微电子元件包括覆盖衬底的主表面的接触焊盘。 接触垫在接触表面具有包含铜的组成。 还提供覆盖在基底的主表面上的钝化层。 钝化层覆盖接触焊盘，使得其暴露接触表面的至少一部分。 布置在堆叠中的多个金属层覆盖在接触表面和钝化层的至少一部分上。 堆叠包括多层，其可以具有不同的厚度和不同的金属，其中最低层包括与接触表面接触的钛（Ti）和镍（Ni）。

公开(公告)号：US20080017984A1

公开(公告)日：2008-01-24

申请号：US11459119

申请日：2006-07-21

Applicant: Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

Inventor： Mukta G. Farooq ,  Tien-Jen Cheng ,  Roger A. Quon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A microelectronic element and a related method for fabricating such is provided. The microelectronic element comprises a contact pad overlying a major surface of a substrate. The contact pad has a composition including copper at a contact surface. A passivation layer is also provided overlying the major surface of the substrate. The passivation layer overlies the contact pad such that it exposes at least a portion of the contact surface. A plurality of metal layers arranged in a stack overlie the contact surface and at least a portion of the passivation layer. The stack includes multiple layers, which can have different thicknesses and different metals, with the lowest layer including titanium (Ti) and nickel (Ni) in contact with the contact surface.

Abstract translation: 提供微电子元件及其制造方法。 微电子元件包括覆盖衬底的主表面的接触焊盘。 接触垫在接触表面具有包含铜的组成。 还提供覆盖在基底的主表面上的钝化层。 钝化层覆盖接触焊盘，使得其暴露接触表面的至少一部分。 布置在堆叠中的多个金属层覆盖在接触表面和钝化层的至少一部分上。 堆叠包括多层，其可以具有不同的厚度和不同的金属，其中最低层包括与接触表面接触的钛（Ti）和镍（Ni）。