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31.发明申请公开(公告)号：US20130249118A1
公开(公告)日：2013-09-26
申请号：US13428251
申请日：2012-03-23
IPC分类号： H01L23/485 , H01L21/60
CPC分类号： H01L23/49816 , H01L21/4828 , H01L23/49827 , H01L23/49833 , H01L23/49861 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/81 , H01L24/96 , H01L25/0657 , H01L25/105 , H01L2224/16245 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48177 , H01L2224/73265 , H01L2224/81191 , H01L2224/81815 , H01L2224/8385 , H01L2224/96 , H01L2225/0651 , H01L2225/06517 , H01L2225/06572 , H01L2225/1029 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/16152 , H01L2924/181 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.
摘要翻译： 一种集成电路封装系统的制造方法，包括：形成具有终端和电路端的导电迹线; 在终端上形成终端; 将集成电路芯片直接连接在导电迹线的电路端，集成电路芯片从端子侧向偏移，集成电路芯片的有源侧面向电路端; 并在端子和集成电路管芯上形成绝缘层，由绝缘层覆盖集成电路管芯。
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32.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD AND METHOD OF MANUFACTURE THEREOF 有权具有垫片的集成电路包装系统及其制造方法公开(公告)号：US20130154072A1
公开(公告)日：2013-06-20
申请号：US13326173
申请日：2011-12-14
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L23/49548 , H01L21/4832 , H01L23/3121 , H01L23/49541 , H01L23/49558 , H01L23/49582 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/05554 , H01L2224/131 , H01L2224/16225 , H01L2224/29099 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/01327 , H01L2924/10253 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, and a peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; and applying an insulation layer directly on a distribution layer bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge with a cavity in the portion of the insulation layer directly below the integrated circuit.
摘要翻译： 一种集成电路封装系统的制造方法，其特征在于，具备：外周引线底面，外周引线顶面，外周引线非水平侧，外周引线水平脊突出的周边引线， 水平面 在外围引线顶侧形成第一顶部分布层; 将集成电路连接到第一顶部分布层; 并且绝缘层直接施加在第一顶部分布层的分布层底部范围和周边引线水平脊的周围引线脊下侧，并且在绝缘层的直接在集成电路下面的部分具有空腔。
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33.发明授权Integrated circuit packaging system with filled vias and method of manufacture thereof 有权具有填充通孔的集成电路封装系统及其制造方法公开(公告)号：US08466057B2
公开(公告)日：2013-06-18
申请号：US13070789
申请日：2011-03-24
IPC分类号： H01L21/4763 , H01L29/40 , H01L29/06
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion.
摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 在基板中形成通孔，具有顶端和底端与底端的通孔大于顶端; 在基板上形成焊盘，焊盘包围通孔的顶端; 并且在所述通孔上回流具有比所述通孔更高的体积的导电填料，所述导电填料具有从所述底端和所述底端延伸的突起与所述突起的至少一个表面完全重叠。
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34.发明授权Semiconductor device and method of forming a shielding layer between stacked semiconductor die 有权半导体器件和在堆叠的半导体管芯之间形成屏蔽层的方法公开(公告)号：US08378383B2
公开(公告)日：2013-02-19
申请号：US12411310
申请日：2009-03-25
IPC分类号： H01L30/134
CPC分类号： H01L23/552 , H01L21/568 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/50 , H01L23/5389 , H01L24/19 , H01L24/48 , H01L24/85 , H01L25/0657 , H01L25/50 , H01L2223/6677 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/12105 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/73203 , H01L2224/73204 , H01L2224/73265 , H01L2224/73267 , H01L2224/85 , H01L2225/06517 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2224/45099 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.
摘要翻译： 半导体器件具有形成在其背面上的屏蔽层的第一半导体管芯。 第一半导体管芯安装到载体上。 在屏蔽层上形成第一绝缘层。 第二半导体管芯安装在由屏蔽层和第一绝缘层隔开的第一半导体管芯上。 在第一和第二半导体管芯上沉积第二绝缘层。 在第二半导体管芯和第二绝缘层上形成第一互连结构。 在第一半导体管芯和第二绝缘层上形成第二互连结构。 屏蔽层通过接合线RDL或TSV与低阻抗接地点电连接。 第二半导体管芯也可以在其背面形成有屏蔽层。 半导体管芯通过金属对金属屏蔽层接合。
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35.发明授权Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices 有权在器件周围的周边区域的凹陷区域中形成导电柱的半导体器件和方法，用于与其他器件的电互连公开(公告)号：US08349657B2
公开(公告)日：2013-01-08
申请号：US13423263
申请日：2012-03-18
申请人： Byung Tai Do , Reza A. Pagaila , Linda Pei Ei Chua
发明人： Byung Tai Do , Reza A. Pagaila , Linda Pei Ei Chua
CPC分类号： H01L23/49816 , H01L21/6835 , H01L21/6836 , H01L23/3107 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/16 , H01L24/48 , H01L25/105 , H01L2221/68327 , H01L2221/68372 , H01L2224/02313 , H01L2224/02333 , H01L2224/03 , H01L2224/0401 , H01L2224/04042 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1308 , H01L2224/13082 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/48137 , H01L2224/4823 , H01L2224/73265 , H01L2224/85399 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19107 , H01L2924/30105 , H01L2224/13099 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor wafer contains a plurality of semiconductor die each having a peripheral area around the die. A first insulating layer is formed over the die. A recessed region with angled sidewall is formed in the peripheral area. A first conductive layer is formed over the first insulating layer outside the recessed region and further into the recessed region. A conductive pillar is formed over the first conductive layer within the recessed region. A second insulating layer is formed over the first insulating layer, conductive pillar, and first conductive layer such that the conductive pillar is exposed from the second insulating layer. A dicing channel partially through the peripheral area. The semiconductor wafer undergoes backgrinding to the dicing channel to singulate the semiconductor wafer and separate the semiconductor die. The semiconductor die can be disposed in a semiconductor package with other components and electrically interconnected through the conductive pillar.
摘要翻译： 半导体晶片包含多个半导体管芯，每个半导体管芯具有围绕管芯的周边区域。 在模具上形成第一绝缘层。 具有成角度侧壁的凹陷区域形成在周边区域中。 第一导电层形成在凹陷区域外部的第一绝缘层的上方，并且进一步进入凹陷区域。 导电柱形成在凹陷区域内的第一导电层的上方。 在第一绝缘层，导电柱和第一导电层上形成第二绝缘层，使得导电柱从第二绝缘层露出。 切割通道部分通过周边区域。 半导体晶片经历对切割通道的后研磨，以切割半导体晶片并分离半导体管芯。 半导体管芯可以被设置在具有其它部件的半导体封装中并通过导电柱电互连。
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36.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ELECTRICAL INTERFACE AND METHOD OF MANUFACTURE THEREOF 有权具有电气接口的集成电路包装系统及其制造方法公开(公告)号：US20120280407A1
公开(公告)日：2012-11-08
申请号：US13102047
申请日：2011-05-05
CPC分类号： H01L23/49811 , H01L21/4832 , H01L21/561 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/48 , H01L24/97 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.
摘要翻译： 一种集成电路封装系统的制造方法，包括：形成具有接触突起的隔离触点，所述接触突起具有下突出表面，上突出表面和突出侧壁; 形成与所述隔离接触件相邻的管芯焊盘，具有管芯焊盘突出部，所述焊盘突起部具有下模具突出表面，上模具突出表面和模具突出侧壁; 将接触垫沉积在接触突起上; 将管芯焊盘沉积在管芯焊盘突起上; 将集成电路管芯耦合到所述接触突起; 以及在所述集成电路管芯上模制封装。
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37.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTED CIRCUIT LEAD ARRAY AND METHOD OF MANUFACTURE THEREOF 有权集成电路封装系统，带引线电路引线阵列及其制造方法公开(公告)号：US20120280390A1
公开(公告)日：2012-11-08
申请号：US13102044
申请日：2011-05-05
IPC分类号： H01L23/488 , H01L21/56 , H01L23/12 , H01L21/58
CPC分类号： H01L23/49503 , H01L21/4832 , H01L23/3107 , H01L23/4952 , H01L23/49524 , H01L23/49534 , H01L23/49548 , H01L23/49582 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/81 , H01L24/83 , H01L24/85 , H01L2224/131 , H01L2224/16245 , H01L2224/2919 , H01L2224/32245 , H01L2224/45144 , H01L2224/48095 , H01L2224/48245 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2924/00014 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/014 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.
摘要翻译： 一种集成电路封装系统的制造方法，包括：提供具有凹部的具有顶部的端子; 在所述凹陷中施加电介质材料，所述电介质材料在其中形成间隙并暴露所述顶部的一部分; 在所述间隙内形成迹线并与所述顶部直接接触，所述迹线在所述电介质材料的上表面上横向延伸; 并通过轨迹将集成电路连接到终端。
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38.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF 有权具有贴片连接的集成电路包装系统及其制造方法公开(公告)号：US20120280377A1
公开(公告)日：2012-11-08
申请号：US13102041
申请日：2011-05-05
IPC分类号： H01L23/495 , H01L21/58
CPC分类号： H01L23/49548 , H01L21/4832 , H01L23/3107 , H01L23/49582 , H01L24/13 , H01L24/16 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/131 , H01L2224/16245 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2224/83385 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92247 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/014 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.
摘要翻译： 一种集成电路封装系统的制造方法，其特征在于，具备：外周引线底面，外周引线顶面，周边引线非水平侧，周边引线水平脊，周边引线导体板等的周边引线， 外围引线水平脊从外围引线非水平侧突出; 在所述外围引线顶侧形成第一顶部分布层，所述第一顶部分布层具有第一顶部端子; 将集成电路连接到第一顶部分布层，所述集成电路具有直接在多个第一顶部终端上的中心部分; 并且将绝缘层直接施加在第一顶部分配层的底部范围和周边引线水平脊的周边引线脊下侧。
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39.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PAD CONNECTION AND METHOD OF MANUFACTURE THEREOF 有权具有贴片连接的集成电路包装系统及其制造方法公开(公告)号：US20120280376A1
公开(公告)日：2012-11-08
申请号：US13426442
申请日：2012-03-21
IPC分类号： H01L23/495 , H01L21/60
CPC分类号： H01L21/4832 , H01L23/3107 , H01L23/49548 , H01L23/49582 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L2224/05554 , H01L2224/16245 , H01L2224/32245 , H01L2224/48247 , H01L2224/73265 , H01L2224/83385 , H01L2224/85439 , H01L2224/85444 , H01L2224/85447 , H01L2224/85455 , H01L2224/85464 , H01L2224/92247 , H01L2924/00014 , H01L2924/01029 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/01028 , H01L2924/01046 , H01L2924/01079 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit.
摘要翻译： 一种集成电路封装系统的制造方法，其特征在于，具备：外周引线底面，外周引线顶面，周边引线非水平侧，周边引线水平脊，周边引线导体板等的周边引线， 外围引线水平脊从外围引线非水平侧突出; 形成邻近外围引线的中心引线; 在外围引线顶侧形成第一顶部分布层; 将集成电路连接到第一顶部分布层; 将绝缘层直接施加在第一顶部分配层的底部范围和周边引线水平脊的周边引线脊下侧; 并将散热器附接到集成电路下的中心引线。
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40.发明申请INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILLED VIAS AND METHOD OF MANUFACTURE THEREOF 有权具有填充VIAS的集成电路包装系统及其制造方法公开(公告)号：US20120241973A1
公开(公告)日：2012-09-27
申请号：US13070789
申请日：2011-03-24
CPC分类号： H01L23/3128 , H01L24/16 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05554 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/00013 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/3511 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a via hole in the substrate, the via hole having a top end and a bottom end with the bottom end is larger than the top end; forming a pad on the substrate, the pad encloses the top end of the via hole; and reflowing a conductive filler having higher volume than the via hole over the via hole, the conductive filler having a protrusion extending from the bottom end and the bottom end entirely overlaps at least one surface of the protrusion.
摘要翻译： 一种集成电路封装系统的制造方法，包括：提供基板; 在基板中形成通孔，具有顶端和底端与底端的通孔大于顶端; 在基板上形成焊盘，焊盘包围通孔的顶端; 并且在所述通孔上回流具有比所述通孔更高的体积的导电填料，所述导电填料具有从所述底端和所述底端延伸的突起与所述突起的至少一个表面完全重叠。
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