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409 条记录 (耗时 0.022 秒)

    Power MOSFET device structure for high frequency applications
    32.
    发明授权
    Power MOSFET device structure for high frequency applications 有权
    功率MOSFET器件结构用于高频应用

    公开(公告)号：US08963233B2

    公开(公告)日：2015-02-24

    申请号：US13436192

    申请日：2012-03-30

    申请人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

    发明人： Anup Bhalla ,  Daniel Ng ,  Tiesheng Li ,  Sik K. Lui

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

    CPC分类号： H01L29/66712 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7827

    摘要： This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.

    摘要翻译： 本发明公开了一种新的开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的半导体的第二表面附近的源极区域。 绝缘栅电极设置在第二表面的顶部，用于控制源极到漏极电流，并且源电极插入到绝缘栅电极中，用于基本上防止栅极电极和绝缘栅极之间的外延区域之间的电场的耦合 栅电极。 源极电极进一步覆盖并延伸在绝缘栅上，用于覆盖半导体的第二表面上的区域以接触源极区。外延层设置在漏极区之上并且具有不同掺杂剂浓度。 栅极通过具有取决于垂直功率器件的Vgsmax额定值的厚度的绝缘层与源电极绝缘。

    TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY
    36.
    发明申请
    TRENCH JUNCTION BARRIER CONTROLLED SCHOTTKY 有权
    TRENCH JUNCTION BARRIER控制的肖特

    公开(公告)号：US20140332882A1

    公开(公告)日：2014-11-13

    申请号：US13892312

    申请日：2013-05-13

    申请人： SiK K. Lui ,  Anup Bhalla

    发明人： SiK K. Lui ,  Anup Bhalla

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/66143 ,  H01L29/66712 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872

    摘要： A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first conductivity type to form a top doped region in a semiconductor substrate of said first conductivity type; 2) providing a trench through the top doped region to a predetermined depth and providing a dopant of the second conductivity type to form a bottom dopant region of the second conductivity type; and 3) lining a Schottky barrier metal layer on a sidewall of the trench at least extending from a bottom of the top doped region to a top of the bottom doped region.

    摘要翻译： 一种用于制造肖特基二极管的方法，包括以下步骤：1）提供具有与第一导电类型相反的第二导电类型的掺杂剂的区域，以在所述第一导电类型的半导体衬底中形成顶部掺杂区域; 2）通过顶部掺杂区域提供沟槽至预定深度并提供第二导电类型的掺杂剂以形成第二导电类型的底部掺杂区域; 以及3）将至少从顶部掺杂区域的底部延伸到底部掺杂区域的顶部的沟槽的侧壁上的肖特基势垒金属层衬里。

    Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method
    39.
    发明申请
    Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
    具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法

    公开(公告)号：US20140167212A1

    公开(公告)日：2014-06-19

    申请号：US13712980

    申请日：2012-12-13

    申请人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

    发明人： Xiaobin Wang ,  Anup Bhalla ,  Hamza Yilmaz ,  Daniel Ng

    IPC分类号： H01L21/762 ,  H01L29/06

    CPC分类号： H01L29/407 ,  H01L21/76205 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.

    摘要翻译： 公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。 在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到 星展集团