公开(公告)号：US09018744B2

公开(公告)日：2015-04-28

申请号：US13626830

申请日：2012-09-25

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Khalil Hosseini

IPC: H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/498 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Abstract translation: 半导体器件包括载体。 此外，半导体器件包括半导体芯片，其包括第一主表面和与第一主表面相对的第二主表面，其中第一电极布置在第一主表面上，并且半导体芯片安装在载体上，第二主体 面向载体的表面。 此外，提供了嵌入半导体芯片的封装体。 半导体器件还包括接触夹，其中接触夹是具有接合到第一电极并具有形成半导体器件的外部端子的端子部分的接合部分的整体部分。

公开(公告)号：US20150028487A1

公开(公告)日：2015-01-29

申请号：US13951554

申请日：2013-07-26

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L25/04

CPC classification number: H01L25/04 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure.

Abstract translation: 芯片封装器件包括导电芯片载体，至少一个连接到导电芯片载体的半导体芯片，以及嵌入芯片载体，至少一个半导体芯片和无源电子器件的绝缘叠层结构。 无源电子器件包括第一结构导电层，第一结构化导电层在层压结构的表面上延伸。

公开(公告)号：US20140151862A1

公开(公告)日：2014-06-05

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

公开(公告)号：US20140084433A1

公开(公告)日：2014-03-27

申请号：US13626830

申请日：2012-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Khalil Hosseini

IPC: H01L21/56 ,  H01L23/498

CPC classification number: H01L21/56 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/498 ,  H01L24/34 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37164 ,  H01L2224/37169 ,  H01L2224/37599 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device.

Abstract translation: 半导体器件包括载体。 此外，半导体器件包括半导体芯片，其包括第一主表面和与第一主表面相对的第二主表面，其中第一电极布置在第一主表面上，并且半导体芯片安装在载体上，第二主体 面向载体的表面。 此外，提供了嵌入半导体芯片的封装体。 半导体器件还包括接触夹，其中接触夹是具有接合到第一电极并具有形成半导体器件的外部端子的端子部分的接合部分的整体部分。

公开(公告)号：US20130328197A1

公开(公告)日：2013-12-12

申请号：US13966320

申请日：2013-08-14

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Matthias Stecher

IPC: H01L23/532

CPC classification number: H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/2075 ,  H01L2924/00012 ,  H01L2924/01006

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract translation: 公开了一种用于生产的电子设备和方法。 一个实施例提供了一种集成部件，其具有由铜或铜合金构成的第一层或者包含铜或铜合金的第一层，并且具有导电的第二层，其材料与第一层的材料不同， 设置在第一层和第二层上。

公开(公告)号：US09397018B2

公开(公告)日：2016-07-19

申请号：US13742456

申请日：2013-01-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/373 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/06 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/29 ,  H01L21/56 ,  H01L23/06 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

Abstract translation: 提供了芯片布置，芯片布置包括载体; 至少一个芯片电连接到载体顶侧; 至少部分地围绕所述至少一个芯片和所述载体顶侧的封装材料，其中所述封装材料形成在所述载体的一个或多个侧面上; 以及设置在载体底侧上的至少一个侧面上的陶瓷材料。

公开(公告)号：US09171804B2

公开(公告)日：2015-10-27

申请号：US13681079

申请日：2012-11-19

Applicant: Infineon Technologies AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L21/58 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US09159701B2

公开(公告)日：2015-10-13

申请号：US14028577

申请日：2013-09-17

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/48 ,  H01L21/50 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L23/492 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供了一种制造芯片封装的方法。 该方法可以包括电接触至少一个第一芯片，第一芯片包括第一侧和与第一侧相对的第二侧，其第二侧为导电载体。 绝缘层形成在导电载体的至少一部分上并且在芯片的第一侧的至少一部分上方。 至少一个第二芯片布置在绝缘层上。 在第一芯片和第二芯片上形成封装材料。 电触头通过封装材料形成至少一个第一芯片和至少一个第二芯片的至少一个触点的至少一个触点。

公开(公告)号：US09082767B2

公开(公告)日：2015-07-14

申请号：US14151917

申请日：2014-01-10

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Edward Fuergut ,  Khalil Hosseini ,  Georg Meyer-Berg

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/48 ,  H01L23/28 ,  H01L21/58 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00

Abstract: A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects.

Abstract translation: 提供一种嵌入式集成电路封装，所述嵌入式集成电路封装包括：至少一个布置在芯片载体上的芯片，所述至少一个芯片包括多个芯片接触焊盘; 形成在所述芯片载体上并且至少部分地围绕所述至少一个芯片的封装材料; 通过所述封装材料形成的多个电互连，其中每个电互连电连接到芯片接触焊盘; 以及形成在嵌入式集成电路封装的电互连之间的结构，其中该结构增加了电互连之间的耐爬电阻性。

公开(公告)号：US20150111343A1

公开(公告)日：2015-04-23

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。