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    Phase modulation systems and methods
    31.
    发明授权
    Phase modulation systems and methods 有权

    公开(公告)号：US10594309B2

    公开(公告)日：2020-03-17

    申请号：US16025148

    申请日：2018-07-02

    Applicant: Intel Corporation

    Inventor： Abhishek Agrawal ,  Stefano Pellerano ,  Yanjie Wang ,  Peter Sagazio

    IPC: H03K7/06 ,  H04L27/20

    Abstract: In a phase modulation method enable signals may be sequentially generating based on a clock signal to generate a sequence of enable signals, and a signal is delayed by delay values generated from delay cells based on the sequence of enable signals and digital bit values. A phase modulator may include a first delay circuit configured to: delay a clock signal based on a first delay value to generate a first delayed clock signal, and delay a carrier signal based on the first delayed clock signal to generate a first delayed carrier signal; and a second delay circuit configured to: delay the first delayed clock signal based on a second delay value to generate a second delayed clock signal, and delay the first delayed carrier signal based on the second delayed clock signal to generate a second delayed carrier signal.

    STRIPLINE AND MICROSTRIP TRANSMISSION LINES FOR QUBITS
    32.
    发明申请
    STRIPLINE AND MICROSTRIP TRANSMISSION LINES FOR QUBITS 审中-公开

    公开(公告)号：US20190267692A1

    公开(公告)日：2019-08-29

    申请号：US16320203

    申请日：2016-08-15

    Applicant: Intel Corporation

    Inventor： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Stefano Pellerano

    IPC: H01P3/08 ,  H01P11/00 ,  G06N10/00

    Abstract: Described herein are new transmission line structures for use as resonators and non-resonant interconnects in quantum circuits. In one aspect of the present disclosure, a proposed structure includes a substrate, a ground plane disposed over the substrate, a dielectric layer disposed over the ground plane, and a conductor strip disposed over the dielectric layer. In another aspect, a proposed structure includes a substrate, a lower ground plane disposed over the substrate, a lower dielectric layer disposed over the lower ground plane, a conductor strip disposed over the lower dielectric layer, an upper dielectric layer disposed over the conductor strip, and an upper ground plane disposed over the upper dielectric layer. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to set the frequencies that address individual qubits. Methods for fabricating such structures are disclosed as well.

    Segmented digital-to-time converter calibration
    35.
    发明授权
    Segmented digital-to-time converter calibration 有权
    分段数字到时间转换器校准

    公开(公告)号：US09209958B1

    公开(公告)日：2015-12-08

    申请号：US14318799

    申请日：2014-06-30

    Applicant: Intel Corporation

    Inventor： Georgios Palaskas ,  Paolo Madoglio ,  Stefano Pellerano ,  Ashoke Ravi ,  Kailash Chandrashekar

    IPC: H03K7/06 ,  H03C3/00 ,  H04L27/12 ,  H04L7/00 ,  H04B17/21

    CPC classification number: H04L7/0004 ,  G04F10/005 ,  H04B17/14 ,  H04B17/21 ,  H04L7/0087

    Abstract: This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

    Abstract translation: 该应用程序除其他外还讨论了用于改善数字 - 时间转换器（DTC）的非线性的校准系统。 在一个示例中，校准系统可以包括被配置为表示DTC的段的校准路径，配置成接收校准路径的输出和经处理的频率信息的时间到数字电路，并且提供定时误差信息 并且校准引擎被配置为从主控制器接收控制器调制信息，以向DTC提供校准调制信息以接收定时误差信息，并且使用定时误差向耦合到DTC的校正电路提供补偿信息 信息。

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