公开(公告)号：US20130119552A1

公开(公告)日：2013-05-16

申请号：US13298126

申请日：2011-11-16

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Jui-Pin Hung ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06593 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00

Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.

Abstract translation: 一种器件包括底部芯片和结合到底部芯片的有源顶部管芯。 虚设裸片连接到底部芯片。 虚设裸片与底部芯片电绝缘。

公开(公告)号：US20130115854A1

公开(公告)日：2013-05-09

申请号：US13290879

申请日：2011-11-07

Applicant: Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Yi-Chao Mao ,  Jui-Pin Hung ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B24B49/10

CPC classification number: H01L22/26 ,  B24B7/228 ,  B24B37/013 ,  B24B49/10 ,  H01L22/12 ,  H01L23/3114 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the proceeding of the grinding process, wheel loadings of the grinding process are measured. The grinding process is stopped after the target wheel loading is reached. The method alternatively includes selecting a target reflectivity of wafer grinding processes, and performing a grinding process on a wafer. With a proceeding of the grinding process, reflectivities of a light reflected from a surface of the wafer are measured. The grinding process is stopped after one of the reflectivities reaches the target reflectivity.

Abstract translation: 执行磨削的方法包括：选择用于晶片研磨工艺的目标轮加载，以及对晶片进行研磨处理。 随着研磨过程的进行，测量研磨过程的轮载荷。 在达到目标轮加载后停止研磨过程。 该方法或者包括选择晶片研磨过程的目标反射率，以及对晶片进行研磨处理。 随着研磨过程的进行，测量从晶片表面反射的光的反射率。 在一个反射率达到目标反射率之后停止研磨过程。

公开(公告)号：US08395221B2

公开(公告)日：2013-03-12

申请号：US12854638

申请日：2010-08-11

Applicant: Jing-Cheng Lin ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu

IPC: H01L21/70

CPC classification number: H01L21/823842 ,  H01L21/2254 ,  H01L21/28035 ,  H01L29/4925 ,  H01L29/6659

Abstract: A semiconductor device and a method of manufacturing are provided. A dielectric layer is formed over a substrate, and a first silicon-containing layer, undoped, is formed over the dielectric layer. Atomic-layer doping is used to dope the undoped silicon-containing layer. A second silicon-containing layer is formed over first silicon-containing layer. The process may be expanded to include forming a PMOS and NMOS device on the same wafer. For example, the first silicon-containing layer may be thinned in the PMOS region prior to the atomic-layer doping. In the NMOS region, the doped portion of the first silicon-containing layer is removed such that the remaining portion of the first silicon-containing layer in the NMOS is undoped. Thereafter, another atomic-layer doping process may be used to dope the first silicon-containing layer in the NMOS region to a different conductivity type. A third silicon-containing layer may be formed doped to the respective conductivity type.

Abstract translation: 提供半导体器件和制造方法。 介电层形成在衬底上，并且在介电层上形成未掺杂的第一含硅层。 原子层掺杂用于掺杂未掺杂的含硅层。 在第一含硅层上形成第二含硅层。 该过程可以扩展到包括在同一晶片上形成PMOS和NMOS器件。 例如，在原子层掺杂之前，第一含硅层可以在PMOS区中减薄。 在NMOS区域中，去除第一含硅层的掺杂部分，使得NMOS中的第一含硅层的剩余部分未掺杂。 此后，可以使用另一种原子层掺杂工艺将NMOS区域中的第一含硅层掺杂到不同的导电类型。 可以形成掺杂到相应导电类型的第三含硅层。

公开(公告)号：US20130049195A1

公开(公告)日：2013-02-28

申请号：US13215959

申请日：2011-08-23

Applicant: Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/488 ,  H01L21/78

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/85 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method includes performing a laser grooving to remove a dielectric material in a wafer to form a trench, wherein the trench extends from a top surface of the wafer to stop at an intermediate level between the top surface and a bottom surface of the wafer. The trench is in a scribe line between two neighboring chips in the wafer. A polymer is filled into the trench and then cured. After the step of curing the polymer, a die saw is performed to separate the two neighboring chips, wherein a kerf line of the die saw cuts through a portion of the polymer filled in the trench.

Abstract translation: 一种方法包括执行激光切槽以去除晶片中的电介质材料以形成沟槽，其中沟槽从晶片的顶表面延伸以在晶片的顶表面和底表面之间的中间水平处停止。 沟槽在晶片中的两个相邻芯片之间的划线中。 将聚合物填充到沟槽中，然后固化。 在固化聚合物的步骤之后，执行模锯以分离两个相邻的芯片，其中模具的切口线切割填充在沟槽中的聚合物的一部分。

公开(公告)号：US08361842B2

公开(公告)日：2013-01-29

申请号：US12880736

申请日：2010-09-13

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin

IPC: H01L21/50

CPC classification number: H01L24/81 ,  H01L21/561 ,  H01L21/568 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L25/0655 ,  H01L2221/68327 ,  H01L2224/0233 ,  H01L2224/02333 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/13 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Abstract translation: 一种方法包括提供载体上设置有粘合层; 以及提供包括第一表面，与第一表面相对的第二表面的模具。 模具还包括与第二表面相邻的多个接合焊盘; 以及多个接合焊盘上的介电层。 该方法还包括将模具放置在粘合剂层上，其中第一表面面向粘合剂层，电介质层背向粘合剂层; 形成模塑料以覆盖模具，其中模塑料围绕模具; 将模塑料的一部分直接在模具上去除以暴露介电层; 以及在所述模制化合物上形成再分配线，并通过所述介电层电耦合到所述多个键合焊盘之一。

公开(公告)号：US08319349B2

公开(公告)日：2012-11-27

申请号：US13342583

申请日：2012-01-03

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Hung-Jung Tu

IPC: H01L23/48

CPC classification number: H01L21/561 ,  H01L21/486 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.

公开(公告)号：US20120128457A1

公开(公告)日：2012-05-24

申请号：US12954180

申请日：2010-11-24

Applicant: Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Hsin Chang ,  Hsin-Yu Chen ,  Fang Wen Tsai ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B65G1/133 ,  B25J18/00

CPC classification number: H01L21/6875 ,  B65G47/90 ,  H01L21/68707 ,  Y10T74/20305

Abstract: An apparatus includes a robot arm, and a plurality of guide pins mounted on the robot arm. Each of the plurality of guide pins includes a plurality of wafer supports at different levels, with each of the plurality of wafer supports configured to support and center a wafer having a size different from wafers configured to be supported and centered by remaining ones of the plurality of wafer supports

Abstract translation: 一种装置包括机器人臂和安装在机器人手臂上的多个引导销。 多个引导销中的每一个包括多个不同级别的晶片支架，其中多个晶片支撑件中的每一个被配置为支撑和定心具有不同晶圆尺寸的晶片，所述晶片被配置为被多个晶圆支撑的中心部分支撑并居中 的晶片支架

公开(公告)号：US20120045611A1

公开(公告)日：2012-02-23

申请号：US12858211

申请日：2010-08-17

Applicant: Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/12 ,  B32B3/24 ,  B32B3/26 ,  B32B38/10 ,  H01L21/50 ,  B32B37/02 ,  B32B37/12 ,  B32B17/06 ,  B32B7/12

CPC classification number: G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

Abstract translation: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US20120025368A1

公开(公告)日：2012-02-02

申请号：US12847802

申请日：2010-07-30

Applicant: Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Yan-Fu Lin ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/11 ,  H01L24/81 ,  H01L2223/54413 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: A system and method for determining underfill expansion is provided. An embodiment comprises forming cover marks along a top surface of a substrate, attaching a semiconductor substrate to the top surface of the substrate, placing an underfill material between the semiconductor substrate and the substrate, and then using the cover marks to determine the expansion of the underfill over the top surface of the substrate. Additionally, cover marks may also be formed along a top surface of the semiconductor substrate, and the cover marks on both the substrate and the semiconductor substrate may be used together as alignment marks during the alignment of the substrate and the semiconductor substrate.

Abstract translation: 提供了一种用于确定底部填充膨胀的系统和方法。 一个实施例包括沿着衬底的顶表面形成覆盖标记，将半导体衬底附接到衬底的顶表面，将底部填充材料放置在半导体衬底和衬底之间，然后使用覆盖标记来确定 底部填充在基材的顶表面上。 此外，也可以沿着半导体衬底的顶表面形成覆盖标记，并且衬底和半导体衬底上的覆盖标记可以在衬底和半导体衬底的对准期间一起用作对准标记。

公开(公告)号：US20110316201A1

公开(公告)日：2011-12-29

申请号：US12822880

申请日：2010-06-24

Applicant: Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Lin-Chih Huang ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: B06B1/00 ,  H01L21/56 ,  B29C45/07

CPC classification number: H01L21/56 ,  H01L21/561 ,  H01L24/94 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00

Abstract: In accordance with an embodiment, a molding apparatus comprises a screen having a planar top surface; a recess in the screen and extending below the planar top surface; a blade capable of traversing the planar top surface; and a molding compound applicator. Another embodiment is a method for molding. The method comprises providing a substrate in a confined volume with an open top surface, applying molding compound in the confined volume, and traversing the open top surface with a blade thereby forming the molding compound to have a planar surface that is co-planar with the open top surface. The substrate has at least one semiconductor die adhered to the substrate.

Abstract translation: 根据实施例，成型设备包括具有平坦顶表面的筛网; 屏幕中的凹槽并在平面顶表面下方延伸; 能够穿过平面顶表面的刀片; 和模塑料涂布器。 另一实施例是一种模制方法。 该方法包括在约束体积中提供具有敞开顶部表面的基底，在约束体积中施加模塑料，并用刀片横穿开放的顶部表面，从而形成模制化合物以具有与该平坦表面共面的平坦表面 开顶表面。 衬底具有至少一个半导体管芯粘附到衬底上。