公开(公告)号：US06618938B1

公开(公告)日：2003-09-16

申请号：US09974157

申请日：2001-10-09

申请人： Maniam Alagaratnam ,  Kishor V. Desai ,  Sunil A. Patel

发明人： Maniam Alagaratnam ,  Kishor V. Desai ,  Sunil A. Patel

IPC分类号： H05K334

CPC分类号： H05K3/3436 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K3/284 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/041 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/53174 ,  H01L2224/0401

摘要： The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate. Advantageously, the improved thermal performance of the present invention may allow larger substrates, larger dies, larger solder ball arrays, reduced solder ball pitches and pin counts well above conventional levels without compromising semiconductor device reliability.

公开(公告)号：US06552264B2

公开(公告)日：2003-04-22

申请号：US09041580

申请日：1998-03-11

申请人： Timothy F. Carden ,  Glenn O. Dearing ,  Kishor V. Desai ,  Stephen R. Engle ,  Randall Stutzman ,  George H. Thiel

发明人： Timothy F. Carden ,  Glenn O. Dearing ,  Kishor V. Desai ,  Stephen R. Engle ,  Randall Stutzman ,  George H. Thiel

IPC分类号： H01L2302

CPC分类号： H01L23/10 ,  H01L21/50 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/16195 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169

摘要： A chip carrier package that includes a cover plate attached to the stiffener by a reflowable bonding material is disclosed. Additionally, a thermally and electrically conductive bonding material between the cover plate and the chip itself may be included. Also a chip package including an alignment device to aid in properly aligning the cover plate on the stiffener. Furthermore, a method of packaging a chip including providing a reflowable material between the cover plate and stiffener body for attaching the cover plate to the stiffener, and simultaneously attaching the cover plate to the stiffener with an attaching of the carrier to an electronic circuit board.

摘要翻译： 公开了一种芯片载体封装，其包括通过可回流接合材料附接到加强件的盖板。 此外，可以包括在盖板和芯片本身之间的导热和导电的接合材料。 还有一种芯片封装，其包括对准装置，以帮助正确对准加强件上的盖板。 此外，一种包装芯片的方法，包括在盖板和加强体之间提供可回流材料，用于将盖板附接到加强件，并且同时将盖板附接到加强件，并将托架附接到电子电路板。

公开(公告)号：US06431432B1

公开(公告)日：2002-08-13

申请号：US09596039

申请日：2000-06-15

申请人： John Pierre McCormick ,  Kishor V. Desai

发明人： John Pierre McCormick ,  Kishor V. Desai

IPC分类号： B23K3102

CPC分类号： H01L24/13 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/282 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/10674 ,  H05K2203/0315 ,  H01L2224/29099 ,  H01L2224/0401

摘要： A solder mask is placed on a substrate but this solder mask is used to control solder spread but merely helps to protect traces that are distant from the bond pads. The solder mask has an opening that is preferably greater than the area of a die to be attached; this opening exposes both the bond pads and at least portions of traces proximate to the bond pads. The portions of the traces that are proximate to the bond pads are oxidized, thereby preventing solder from flowing onto these portions of the traces during the solder reflow process.

摘要翻译： 焊接掩模放置在基板上，但是该焊接掩模用于控制焊料扩散，但仅有助于保护远离焊盘的迹线。 焊接掩模具有优选大于要附接的管芯的面积的开口; 该开口暴露接合焊盘和靠近接合焊盘的迹线的至少部分。 靠近接合焊盘的迹线部分被氧化，从而防止焊料在回流焊过程中流到迹线的这些部分上。

公开(公告)号：US06281581B1

公开(公告)日：2001-08-28

申请号：US09388753

申请日：1999-09-02

申请人： Kishor V. Desai ,  Amit K. Sarkhel

发明人： Kishor V. Desai ,  Amit K. Sarkhel

IPC分类号： H01L2144

CPC分类号： H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

摘要： An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

摘要翻译： 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 阶梯式或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。

公开(公告)号：US5880590A

公开(公告)日：1999-03-09

申请号：US852770

申请日：1997-05-07

申请人： Kishor V. Desai ,  Joseph Hromek

发明人： Kishor V. Desai ,  Joseph Hromek

IPC分类号： G01R31/26 ,  G01R1/073 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L23/32 ,  G01R31/02 ,  H01R9/09 ,  H01R23/68 ,  H05K1/11

CPC分类号： G01R31/2863 ,  G01R1/07314 ,  H01L2224/13

摘要： Temporary connections are formed to a flip-chip style chip having solder bumps or preforms protruding therefrom for testing and burn-in while avoiding distortion of the solder bumps or preforms and avoiding wear and damage to a test or burn-in jig such as a ball grid array by the use of a preferably resilient bucketed interposer which includes recesses which have a depth greater than the protrusion of the solder bumps or preforms and, preferably are narrowed at one side to a tear-drop shape. Metallization in the recesses and contacts on the interposer which mate with the test or burn-in jig are preferably textured with dendrites to be self-cleaning. A bevelled tongue and groove arrangement translates a slight compressive force to a slight shearing force between the interposer and the chip to ensure good connections to the protruding solder bumps or preforms on the chip. Any deformation of the solder bumps or preforms thus tends to only improve accuracy of positioning of the solder bumps or preforms and avoids solder voiding due to compression distortion of the solder bumps or preforms. Full burn-in and functional testing can then identify "known good" chips or dies before package completion, particularly to avoid rework of modular circuit packages.

摘要翻译： 临时连接形成为具有从其突出的焊料凸块或预成型件的倒装芯片式芯片，用于测试和老化，同时避免焊料凸块或预制件的变形，并避免对测试或老化夹具（例如球）的磨损和损坏 通过使用优选弹性的桶式插入器，其包括具有大于焊料凸块或预成型件的突出部的深度的凹部，并且优选地在一侧变窄为泪滴形状。 与测试或老化夹具配合的插入物上的凹部和触点中的金属化优选用枝晶进行纹理化以进行自清洁。 倾斜的舌槽布置将轻微的压缩力转换成插入件和芯片之间的轻微的剪切力，以确保与芯片上突出的焊料凸起或预成型件的良好连接。 焊料凸点或预成型件的任何变形因此倾向于仅提高焊料凸块或预成型件的定位精度，并避免由于焊料凸块或预制件的压缩变形引起的焊料排空。 完全老化和功能测试可以在包装完成之前确定“已知的”芯片或模具，特别是避免模块化电路封装的返工。

公开(公告)号：US5201451A

公开(公告)日：1993-04-13

申请号：US727047

申请日：1991-07-09

申请人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Endwell ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

发明人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Endwell ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3478 ,  H05K3/363 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K1/141 ,  H05K2201/0215 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/0557

摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled,; leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.

摘要翻译： 公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。 所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑 所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。 该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。 具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。 然后，将该组件加热以回流间隔件的焊料，并拆卸组装夹具。 留下安装在第二级电子封装上的柔性膜半导体芯片载体，其中载体的柔性膜具有所需的平面几何形状。

公开(公告)号：US5199879A

公开(公告)日：1993-04-06

申请号：US840212

申请日：1992-02-24

申请人： Harold Kohn ,  Kishor V. Desai ,  Ronald J. Romanosky ,  George J. Saxenmeyer, Jr. ,  Reinhold E. Tomek ,  James R. Webb

发明人： Harold Kohn ,  Kishor V. Desai ,  Ronald J. Romanosky ,  George J. Saxenmeyer, Jr. ,  Reinhold E. Tomek ,  James R. Webb

IPC分类号： H05K1/14 ,  H01R12/58 ,  H01R24/58 ,  H05K1/11 ,  H05K3/00 ,  H05K3/30 ,  H05K3/32 ,  H05K3/46

CPC分类号： H01R24/58 ,  H05K3/326 ,  H01R2103/00 ,  H05K1/118 ,  H05K2201/091 ,  H05K2201/09809 ,  H05K2201/1059 ,  H05K2201/10704 ,  H05K3/306 ,  H05K3/4691

摘要： An electrical assembly which includes a first circuit member (e.g., TCM) with at least one conductive pin projecting therefrom for being frictionally and electrically engaged by a flexible portion of circuit means of a second circuit member (e.g., PCB). An opening is provided within the PCB relative to the flexible portions such that these portions project at least partly across the opening and frictionally engage respective conductive portions of the pin when inserted within the opening. Each of these flexible portions in turn is part of a circuit layer which may be coupled to respective conductive planes or the like within the PCB, while the respective conductive portions of the pin may in turn be electrically coupled to various conductive layers within/upon the TCM.

摘要翻译： 一种电气组件，其包括具有从其突出的至少一个导电针的第一电路构件（例如TCM），用于由第二电路构件（例如PCB）的电路装置的柔性部分摩擦和电接合。 在PCB内相对于柔性部分设置开口，使得这些部分至少部分地突出穿过开口并且当插入到开口内时摩擦地接合销的相应导电部分。 这些柔性部分中的每一个又是电路层的一部分，其可以耦合到PCB内的相应的导电平面等，而引脚的相应导电部分又可以电连接到/ 中医。

公开(公告)号：US5159535A

公开(公告)日：1992-10-27

申请号：US365326

申请日：1989-06-13

申请人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

发明人： Kishor V. Desai ,  Nelson P. Franchak ,  Robert H. Katyl ,  Harold Kohn ,  Tamar A. Sholtes ,  Vilakkudi G. Veeraraghavan ,  Charles G. Woychik

IPC分类号： H01L21/98 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC分类号： H01L25/50 ,  H01L23/4985 ,  H01L23/5385 ,  H05K3/3478 ,  H05K3/363 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15321 ,  H05K1/141 ,  H05K2201/0215 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10477 ,  H05K2201/10681 ,  H05K2201/10734 ,  H05K2201/10984 ,  H05K2203/0165 ,  H05K2203/0278 ,  H05K2203/041 ,  H05K2203/0557

摘要： Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier on a second level electronic package. The resulting electronic packaging structure includes electrically conductive spacers, such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads on the flexible film semiconductor chip carrier and corresponding bonding pads on the second level electronic package, and which physically support the flexible film of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture comprising a base plate, a pressure insert with a resilient member, and a top plate. The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template having a pattern of openings corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.

摘要翻译： 公开了用于将柔性膜半导体芯片载体安装在第二级电子封装上的方法和装置。 所得到的电子封装结构包括导电间隔物，例如焊球或焊料涂覆的铜球，其将柔性膜半导体芯片载体上的外引线接合焊盘和第二级电子封装上的对应焊盘电互连，并且物理地支撑 所述半导体芯片载体的柔性膜基本上在所述第二级电子封装的表面上方的平面中。 该电子包装结构使用特殊的组装夹具制成，该组装夹具包括基板，具有弹性构件的压力插入件和顶板。 具有附接到其上的间隔物的柔性膜半导体芯片载体被放置在压力插入件的弹性构件上，该压力插入件与顶层和底板之间的第二级电子封装夹紧在一起。 然后，将该组件加热以回流间隔件的焊料，并且组装夹具被拆卸，使得柔性膜半导体芯片载体安装在第二层电子封装上，其中载体的柔性膜根据需要具有平面几何形状。 可以使用具有对应于柔性膜半导体芯片载体上的外引线接合焊盘的图案的开口图案的特殊模板将间隔件附接到柔性膜半导体芯片载体。

公开(公告)号：US4558590A

公开(公告)日：1985-12-17

申请号：US604752

申请日：1984-04-27

申请人： Kishor V. Desai ,  Roupen L. Keusseyan

发明人： Kishor V. Desai ,  Roupen L. Keusseyan

IPC分类号： G01B5/26 ,  G01B7/32 ,  G01B21/28 ,  H01R13/02

CPC分类号： G01B21/28 ,  G01B7/32

摘要： A method to measure the real contact surface area of a connector or pin is disclosed. The pin and the connector is Gold plated. The pin or the connector is coated with platinum. The pin surface and the connector surface actually comprise a multitude of peaks and valleys, termed asperites. If the pin is chosen to be coated with the platinum, the platinum coated pin is mated with a connector. A portion of the pin surface contacts a corresponding portion of the connector surface. The portion of the pin surface and the corresponding portion of the connector surface is termed a real contact surface area. The pin and connector are separated. The platinum formerly adhering to the real contact surface area of the pin is removed and adheres to the real contact surface of the gold plated connector. Using a metallograph or a scanning electron microscope, the real contact surface of the connector or pin is studied and observed. Since the visual image of platinum is substantially different than the visual image of Gold, the real contact surface area of the pin (and of the connector) is readily discernable. Using an image analyzer, the real contact surface area on the pin and on the connector is measured.

摘要翻译： 公开了一种测量连接器或销的实际接触表面积的方法。 引脚和连接器镀金。 引脚或连接器涂有铂。 销表面和连接器表面实际上包括许多峰和谷，称为曲率。 如果选择该引脚来涂覆铂，则铂镀层的引脚与连接器配合。 销表面的一部分接触连接器表面的对应部分。 销表面的部分和连接器表面的相应部分被称为真实的接触表面积。 引脚和连接器分开。 以前粘附在销的真实接触表面区域的铂被去除并粘附到镀金连接器的真实接触表面。 使用金相线或扫描电子显微镜，研究和观察连接器或针的真实接触表面。 由于铂的视觉图像与金的视觉图像显着不同，所以销（和连接器）的真实接触表面积容易辨别。 使用图像分析仪测量引脚和连接器上的实际接触面积。