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    VERIFYING COMPRESSED STREAM FUSED WITH COPY OR TRANSFORM OPERATIONS
    41.
    发明申请
    VERIFYING COMPRESSED STREAM FUSED WITH COPY OR TRANSFORM OPERATIONS 有权

    公开(公告)号：US20230075667A1

    公开(公告)日：2023-03-09

    申请号：US17470089

    申请日：2021-09-09

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Daniel F. Cutter

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  H03M13/09

    Abstract: Methods and apparatus relating to verifying a compressed stream fused with copy or transform operation(s) are described. In an embodiment, compression logic circuitry compresses input data and stores the compressed data in a temporary buffer. The compression logic circuitry determines a first checksum value corresponding to the compressed data stored in the temporary buffer. Decompression logic circuitry performs a decompress-verify operation and a copy operation. The decompress-verify operation decompresses the compressed data stored in the temporary buffer to determine a second checksum value corresponding to the decompressed data from the temporary buffer. The copy operation transfers the compressed data from the temporary buffer to a destination buffer in response to a match between the first checksum value and the second checksum value. Other embodiments are also disclosed and claimed.

    Supporting data compression using match scoring
    42.
    发明授权
    Supporting data compression using match scoring 有权

    公开(公告)号：US10140046B2

    公开(公告)日：2018-11-27

    申请号：US15663328

    申请日：2017-07-28

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/34 ,  G06F3/06 ,  H03M7/40 ,  H03M7/30 ,  G06F8/52 ,  G06F12/1018 ,  G06F12/1027

    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.

    LOOK-AHEAD HASH CHAIN MATCHING FOR DATA COMPRESSION
    47.
    发明申请
    LOOK-AHEAD HASH CHAIN MATCHING FOR DATA COMPRESSION 有权

    公开(公告)号：US20170126248A1

    公开(公告)日：2017-05-04

    申请号：US15406133

    申请日：2017-01-13

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/30 ,  H03M7/42

    CPC classification number: H03M7/3086 ,  H03M7/42

    Abstract: Example data compression methods disclosed herein include determining a first hash chain index corresponding to a first position in an input data buffer based on a first group of bytes accessed from the input data buffer beginning at a first look-ahead offset from the first position. If a first hash chain (indexed by the first hash chain index), does not satisfy a quality condition, a second hash chain index corresponding to the first position in the input data buffer based on a second group of bytes accessed from the input data buffer beginning at a second look-ahead offset from the first position is determined. The input data buffer is searched at respective adjusted buffer positions to find a second string of data bytes matching a first string of data bytes and information related to the second string of data bytes is provided to an encoder to output compressed data.

    Look-ahead hash chain matching for data compression
    49.
    发明授权
    Look-ahead hash chain matching for data compression 有权
    先进的哈希链匹配用于数据压缩

    公开(公告)号：US09584155B1

    公开(公告)日：2017-02-28

    申请号：US14864458

    申请日：2015-09-24

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/00 ,  H03M7/30

    CPC classification number: H03M7/3086 ,  H03M7/42

    Abstract: Example data compression methods disclosed herein include determining a hash chain index corresponding to a first position in an input data buffer based on a group of bytes beginning at a look-ahead offset from the first position. Such disclosed example methods also include, when a hash chain, which is indexed by the hash chain index, satisfies a quality condition, searching the input data buffer at respective adjusted buffer positions corresponding to a set of buffer positions stored in the hash chain being offset by the look-ahead offset to find a second data string matching a first data string beginning at the first position in the input data buffer. Such disclosed example methods further include, when the second data string satisfies a length condition, providing a relative position and a length of the second data string to an encoder to output compressed data corresponding to the input data buffer.

    Abstract translation: 本文公开的示例数据压缩方法包括基于从与第一位置的先行偏移开始的一组字节来确定与输入数据缓冲器中的第一位置相对应的散列链索引。 这样公开的示例性方法还包括当由散列链索引索引的散列链满足质量条件时，在对应于存储在散列链中的一组缓冲位置的相应调整的缓冲位置处搜索输入数据缓冲器， 通过先行偏移来找到与从输入数据缓冲器中的第一位置开始的第一数据串匹配的第二数据串。 这种公开的示例方法还包括当第二数据串满足长度条件时，向编码器提供第二数据串的相对位置和长度以输出对应于输入数据缓冲器的压缩数据。

    Supporting data compression using match scoring
    50.
    发明授权
    Supporting data compression using match scoring 有权
    使用匹配评分支持数据压缩

    公开(公告)号：US09419648B1

    公开(公告)日：2016-08-16

    申请号：US14858752

    申请日：2015-09-18

    Applicant: Intel Corporation

    Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

    IPC: H03M7/40 ,  G06F3/06

    CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0653 ,  G06F3/0673 ,  G06F8/52 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2212/401 ,  G06F2212/68 ,  H03M7/3086 ,  H03M7/40

    Abstract: In one embodiment, a processing system is provided. The processing system includes a memory for storing an input bit stream and a processing logic coupled to the memory. The processing logic to identify, within the input bit stream, a first bit subsequence of an input bit sequence and a second bit subsequence of the input bit sequence. A first score reflecting the length of the first bit subsequence and the distance between the input bit sequence and the first bit subsequence and a second score reflecting the length of the second bit subsequence, within the input bit stream, and the distance between the input bit sequence and the second bit subsequence is determined. In view of the first score and the second score, one of the first bit subsequence or the second bit subsequence is selected. A code representing a selected bit subsequence is appended to an output bit sequence.

    Abstract translation: 在一个实施例中，提供了处理系统。 处理系统包括用于存储输入比特流的存储器和耦合到存储器的处理逻辑。 该处理逻辑在输入比特流内识别输入比特序列的第一比特子序列和输入比特序列的第二比特子序列。 反映第一比特子序列的长度和输入比特序列与第一比特子序列之间的距离的第一分数和反映输入比特流内的第二比特子序列的长度的第二分数以及输入比特序列之间的距离 序列和第二位子序列被确定。 考虑到第一分数和第二分数，选择第一比特子序列或第二比特子序列之一。 表示所选位子序列的代码被附加到输出比特序列。

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